diff mbox series

[v2] net/mlx5: enable hint in async table

Message ID 20230306113652.2311599-1-rongweil@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series [v2] net/mlx5: enable hint in async table |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-broadcom-Performance fail Performance Testing issues
ci/intel-Testing success Testing PASS
ci/iol-intel-Functional fail Functional Testing issues
ci/intel-Functional success Functional PASS
ci/github-robot: build success github build: passed
ci/iol-abi-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-testing success Testing PASS

Commit Message

Rongwei Liu March 6, 2023, 11:36 a.m. UTC 
  Driver gets the hint value from rte_table_attr for async flow.
Parse the value and pass the supported value to hardware accordingly.

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Slava Ovsiienko March 6, 2023, 11:59 a.m. UTC | #1 
> -----Original Message-----
> From: Rongwei Liu <rongweil@nvidia.com>
> Sent: понедельник, 6 марта 2023 г. 13:37
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Subject: [PATCH v2] net/mlx5: enable hint in async table
> 
> Driver gets the hint value from rte_table_attr for async flow.
> Parse the value and pass the supported value to hardware accordingly.
> 
> Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Raslan Darawsheh March 7, 2023, 9:02 a.m. UTC | #2 
Hi,

> -----Original Message-----
> From: Rongwei Liu <rongweil@nvidia.com>
> Sent: Monday, March 6, 2023 1:37 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Subject: [PATCH v2] net/mlx5: enable hint in async table
> 
> Driver gets the hint value from rte_table_attr for async flow.
> Parse the value and pass the supported value to hardware accordingly.
> 
> Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
> ---

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index b67b33bc22..70b8e130e8 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -3098,10 +3098,20 @@  flow_hw_table_create(struct rte_eth_dev *dev,
 	grp = container_of(ge, struct mlx5_flow_group, entry);
 	tbl->grp = grp;
 	/* Prepare matcher information. */
+	matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
 	matcher_attr.priority = attr->flow_attr.priority;
 	matcher_attr.optimize_using_rule_idx = true;
 	matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
 	matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
+	/* Parse hints information. */
+	if (attr->specialize) {
+		if (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
+			matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_WIRE;
+		else if (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
+			matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_VPORT;
+		else
+			DRV_LOG(INFO, "Unsupported hint value %x", attr->specialize);
+	}
 	/* Build the item template. */
 	for (i = 0; i < nb_item_templates; i++) {
 		uint32_t ret;