config: added support for NVIDIA ARM implementer ID
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Commit Message
From: Cliff Burdick <cburdick@nvidia.com>
NVIDIA's Jetson Xavier is an ARM chip with NVIDIA as the implementer ID
and a new part number. This patch adds support for this implementer ID
and the part number.
Signed-off-by: Cliff Burdick <cburdick@nvidia.com>
---
.mailmap | 1 +
config/arm/meson.build | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+)
Comments
> -----Original Message-----
> From: cburdick@nvidia.com <cburdick@nvidia.com>
> Sent: Wednesday, February 22, 2023 1:34 AM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>
> Cc: dev@dpdk.org; Cliff Burdick <cburdick@nvidia.com>
> Subject: [PATCH] config: added support for NVIDIA ARM implementer ID
>
> From: Cliff Burdick <cburdick@nvidia.com>
>
> NVIDIA's Jetson Xavier is an ARM chip with NVIDIA as the implementer ID and a new part
> number. This patch adds support for this implementer ID and the part number.
>
> Signed-off-by: Cliff Burdick <cburdick@nvidia.com>
> ---
> .mailmap | 1 +
> config/arm/meson.build | 21 +++++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/.mailmap b/.mailmap
> index 6a91c11be4..2cb0d9e41b 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -230,6 +230,7 @@ Cian Ferriter <cian.ferriter@intel.com> Ciara Loftus
> <ciara.loftus@intel.com> Ciara Power <ciara.power@intel.com> Claire Murphy
> <claire.k.murphy@intel.com>
> +Cliff Burdick <cburdick@nvidia.com>
> Cody Doucette <doucette@bu.edu>
> Congwen Zhang <zhang.congwen@zte.com.cn> Conor Fogarty <conor.fogarty@intel.com> diff --
> git a/config/arm/meson.build b/config/arm/meson.build index 6442ec9596..6c3de22f16 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -159,6 +159,26 @@ implementer_cavium = {
> }
> }
>
> +implementer_nvidia = {
> + 'description': 'NVIDIA',
> + 'flags': [
> + ['RTE_CACHE_LINE_SIZE', 64]
> + ],
> + 'part_number_config': {
> + '0x4': {
> + 'march': 'armv8-a',
> + 'march_features': ['crc', 'crypto', 'lse'],
> + 'compiler_options': ['-march=armv8-a+crc+lse+simd'],
> + 'flags': [
> + ['RTE_USE_C11_MEM_MODEL', true],
> + ['RTE_MAX_LCORE', 8],
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_MACHINE', '"armv8a"']
> + ]
> + }
> + }
> +}
> +
> implementer_ampere = {
> 'description': 'Ampere Computing',
> 'flags': [
> @@ -261,6 +281,7 @@ implementers = {
> '0x41': implementer_arm,
> '0x43': implementer_cavium,
> '0x48': implementer_hisilicon,
> + '0x4e': implementer_nvidia,
> '0x50': implementer_ampere,
> '0x51': implementer_qualcomm,
> '0x70': implementer_phytium,
> --
> 2.17.1
Only native build is supported with this change. To support cross build, soc section needs to be updated.
The below patch can be referenced:
http://patches.dpdk.org/project/dpdk/patch/20230220084827.3317796-3-rasland@nvidia.com/
@@ -230,6 +230,7 @@ Cian Ferriter <cian.ferriter@intel.com>
Ciara Loftus <ciara.loftus@intel.com>
Ciara Power <ciara.power@intel.com>
Claire Murphy <claire.k.murphy@intel.com>
+Cliff Burdick <cburdick@nvidia.com>
Cody Doucette <doucette@bu.edu>
Congwen Zhang <zhang.congwen@zte.com.cn>
Conor Fogarty <conor.fogarty@intel.com>
@@ -159,6 +159,26 @@ implementer_cavium = {
}
}
+implementer_nvidia = {
+ 'description': 'NVIDIA',
+ 'flags': [
+ ['RTE_CACHE_LINE_SIZE', 64]
+ ],
+ 'part_number_config': {
+ '0x4': {
+ 'march': 'armv8-a',
+ 'march_features': ['crc', 'crypto', 'lse'],
+ 'compiler_options': ['-march=armv8-a+crc+lse+simd'],
+ 'flags': [
+ ['RTE_USE_C11_MEM_MODEL', true],
+ ['RTE_MAX_LCORE', 8],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MACHINE', '"armv8a"']
+ ]
+ }
+ }
+}
+
implementer_ampere = {
'description': 'Ampere Computing',
'flags': [
@@ -261,6 +281,7 @@ implementers = {
'0x41': implementer_arm,
'0x43': implementer_cavium,
'0x48': implementer_hisilicon,
+ '0x4e': implementer_nvidia,
'0x50': implementer_ampere,
'0x51': implementer_qualcomm,
'0x70': implementer_phytium,