Message ID | 20230221070756.3070819-3-michaelba@nvidia.com (mailing list archive) |
---|---|
State | Accepted, archived |
Delegated to: | akhil goyal |
Headers |
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Mon, 20 Feb 2023 23:08:04 -0800 From: Michael Baum <michaelba@nvidia.com> To: <dev@dpdk.org> CC: Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, "Thomas Monjalon" <thomas@monjalon.net>, <stable@dpdk.org> Subject: [PATCH v3 2/8] compress/mlx5: fix wrong output Adler-32 checksum offset Date: Tue, 21 Feb 2023 09:07:50 +0200 Message-ID: <20230221070756.3070819-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221070756.3070819-1-michaelba@nvidia.com> References: <20230202162537.1067595-1-michaelba@nvidia.com> <20230221070756.3070819-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT010:EE_|PH0PR12MB7840:EE_ X-MS-Office365-Filtering-Correlation-Id: 4261ccad-2797-4b6b-6f37-08db13da67b9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
compress/mlx5: add LZ4 support
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Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | success | coding style OK |
Commit Message
Michael Baum
Feb. 21, 2023, 7:07 a.m. UTC
After de/compress dequeue, the output checksum is copied into the op structure. The "output_checksum" field in op structure is "uint64_t" type, and the 32-bit checksums (CRC32, Adler-32) are copied into the lower 32 bits. When both CRC32 and Adler-32 are configured, CRC32 is copied into the lower 32 bits and Adler-32 into the upper 32 bits. However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the upper 32 bits. This patch updates Adler-32 output checksun to be copied into the lower 32 bits. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> --- drivers/compress/mlx5/mlx5_compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 06d1ff5b95..82088a7b8c 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, break; case RTE_COMP_CHECKSUM_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 - (opaq[idx].adler32) << 32; + (opaq[idx].adler32); break; case RTE_COMP_CHECKSUM_CRC32_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32