[RFC,v3,07/10] net/gve: support basic stats for DQO
Checks
Commit Message
Add basic stats support for DQO.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Rushil Gupta <rushilg@google.com>
Signed-off-by: Jordan Kimbrough <jrkim@google.com>
Signed-off-by: Jeroen de Borst <jeroendb@google.com>
---
drivers/net/gve/gve_ethdev.c | 2 ++
drivers/net/gve/gve_rx_dqo.c | 12 +++++++++++-
drivers/net/gve/gve_tx_dqo.c | 6 ++++++
3 files changed, 19 insertions(+), 1 deletion(-)
Comments
> -----Original Message-----
> From: Junfeng Guo <junfeng.guo@intel.com>
> Sent: Friday, February 17, 2023 1:32 AM
> To: qi.z.zhang@intel.com; jingjing.wu@intel.com; ferruh.yigit@amd.com;
> beilei.xing@intel.com
> Cc: dev@dpdk.org; xiaoyun.li@intel.com; helin.zhang@intel.com; Junfeng
> Guo <junfeng.guo@intel.com>; Rushil Gupta <rushilg@google.com>; Jordan
> Kimbrough <jrkim@google.com>; Jeroen de Borst <jeroendb@google.com>
> Subject: [RFC v3 07/10] net/gve: support basic stats for DQO
>
> Add basic stats support for DQO.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> Signed-off-by: Rushil Gupta <rushilg@google.com>
> Signed-off-by: Jordan Kimbrough <jrkim@google.com>
> Signed-off-by: Jeroen de Borst <jeroendb@google.com>
> ---
> drivers/net/gve/gve_ethdev.c | 2 ++
> drivers/net/gve/gve_rx_dqo.c | 12 +++++++++++-
> drivers/net/gve/gve_tx_dqo.c | 6 ++++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
> index 1c9d272c2b..2541738da1 100644
> --- a/drivers/net/gve/gve_ethdev.c
> +++ b/drivers/net/gve/gve_ethdev.c
> @@ -481,6 +481,8 @@ static const struct eth_dev_ops
> gve_eth_dev_ops_dqo = {
> .rx_queue_release = gve_rx_queue_release_dqo,
> .tx_queue_release = gve_tx_queue_release_dqo,
> .link_update = gve_link_update,
> + .stats_get = gve_dev_stats_get,
> + .stats_reset = gve_dev_stats_reset,
^^^^^^^^^^^^^^^^^^ I do not see this function in this patch
> .mtu_set = gve_dev_mtu_set,
> };
>
> diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
> index a281b237a4..2a540b1ba5 100644
> --- a/drivers/net/gve/gve_rx_dqo.c
> +++ b/drivers/net/gve/gve_rx_dqo.c
> @@ -37,6 +37,7 @@ gve_rx_refill_dqo(struct gve_rx_queue *rxq)
> next_avail = 0;
> rxq->nb_rx_hold -= delta;
> } else {
> + rxq->no_mbufs += nb_desc - next_avail;
> dev = &rte_eth_devices[rxq->port_id];
> dev->data->rx_mbuf_alloc_failed += nb_desc -
> next_avail;
> PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed
> port_id=%u queue_id=%u", @@ -57,6 +58,7 @@ gve_rx_refill_dqo(struct
> gve_rx_queue *rxq)
> next_avail += nb_refill;
> rxq->nb_rx_hold -= nb_refill;
> } else {
> + rxq->no_mbufs += nb_desc - next_avail;
> dev = &rte_eth_devices[rxq->port_id];
> dev->data->rx_mbuf_alloc_failed += nb_desc -
> next_avail;
> PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed
> port_id=%u queue_id=%u", @@ -80,7 +82,9 @@ gve_rx_burst_dqo(void
> *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
> uint16_t pkt_len;
> uint16_t rx_id;
> uint16_t nb_rx;
> + uint64_t bytes;
>
> + bytes = 0;
> nb_rx = 0;
> rxq = rx_queue;
> rx_id = rxq->rx_tail;
> @@ -94,8 +98,10 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf
> **rx_pkts, uint16_t nb_pkts)
> if (rx_desc->generation != rxq->cur_gen_bit)
> break;
>
> - if (unlikely(rx_desc->rx_error))
> + if (unlikely(rx_desc->rx_error)) {
> + rxq->errors++;
> continue;
> + }
>
> pkt_len = rx_desc->packet_len;
>
> @@ -120,6 +126,7 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf
> **rx_pkts, uint16_t nb_pkts)
> rxm->hash.rss = rte_be_to_cpu_32(rx_desc->hash);
>
> rx_pkts[nb_rx++] = rxm;
> + bytes += pkt_len;
> }
>
> if (nb_rx > 0) {
> @@ -128,6 +135,9 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf
> **rx_pkts, uint16_t nb_pkts)
> rxq->next_avail = rx_id_bufq;
>
> gve_rx_refill_dqo(rxq);
> +
> + rxq->packets += nb_rx;
> + rxq->bytes += bytes;
> }
>
> return nb_rx;
> diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
> index af43ff870a..450cf71a6b 100644
> --- a/drivers/net/gve/gve_tx_dqo.c
> +++ b/drivers/net/gve/gve_tx_dqo.c
> @@ -80,10 +80,12 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf
> **tx_pkts, uint16_t nb_pkts)
> uint16_t nb_used;
> uint16_t tx_id;
> uint16_t sw_id;
> + uint64_t bytes;
>
> sw_ring = txq->sw_ring;
> txr = txq->tx_ring;
>
> + bytes = 0;
> mask = txq->nb_tx_desc - 1;
> sw_mask = txq->sw_size - 1;
> tx_id = txq->tx_tail;
> @@ -118,6 +120,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf
> **tx_pkts, uint16_t nb_pkts)
> tx_id = (tx_id + 1) & mask;
> sw_id = (sw_id + 1) & sw_mask;
>
> + bytes += tx_pkt->pkt_len;
> tx_pkt = tx_pkt->next;
> } while (tx_pkt);
>
> @@ -141,6 +144,9 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf
> **tx_pkts, uint16_t nb_pkts)
> rte_write32(tx_id, txq->qtx_tail);
> txq->tx_tail = tx_id;
> txq->sw_tail = sw_id;
> +
> + txq->packets += nb_tx;
> + txq->bytes += bytes;
> }
>
> return nb_tx;
> --
> 2.34.1
@@ -481,6 +481,8 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo = {
.rx_queue_release = gve_rx_queue_release_dqo,
.tx_queue_release = gve_tx_queue_release_dqo,
.link_update = gve_link_update,
+ .stats_get = gve_dev_stats_get,
+ .stats_reset = gve_dev_stats_reset,
.mtu_set = gve_dev_mtu_set,
};
@@ -37,6 +37,7 @@ gve_rx_refill_dqo(struct gve_rx_queue *rxq)
next_avail = 0;
rxq->nb_rx_hold -= delta;
} else {
+ rxq->no_mbufs += nb_desc - next_avail;
dev = &rte_eth_devices[rxq->port_id];
dev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;
PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed port_id=%u queue_id=%u",
@@ -57,6 +58,7 @@ gve_rx_refill_dqo(struct gve_rx_queue *rxq)
next_avail += nb_refill;
rxq->nb_rx_hold -= nb_refill;
} else {
+ rxq->no_mbufs += nb_desc - next_avail;
dev = &rte_eth_devices[rxq->port_id];
dev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;
PMD_DRV_LOG(DEBUG, "RX mbuf alloc failed port_id=%u queue_id=%u",
@@ -80,7 +82,9 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
uint16_t pkt_len;
uint16_t rx_id;
uint16_t nb_rx;
+ uint64_t bytes;
+ bytes = 0;
nb_rx = 0;
rxq = rx_queue;
rx_id = rxq->rx_tail;
@@ -94,8 +98,10 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
if (rx_desc->generation != rxq->cur_gen_bit)
break;
- if (unlikely(rx_desc->rx_error))
+ if (unlikely(rx_desc->rx_error)) {
+ rxq->errors++;
continue;
+ }
pkt_len = rx_desc->packet_len;
@@ -120,6 +126,7 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
rxm->hash.rss = rte_be_to_cpu_32(rx_desc->hash);
rx_pkts[nb_rx++] = rxm;
+ bytes += pkt_len;
}
if (nb_rx > 0) {
@@ -128,6 +135,9 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
rxq->next_avail = rx_id_bufq;
gve_rx_refill_dqo(rxq);
+
+ rxq->packets += nb_rx;
+ rxq->bytes += bytes;
}
return nb_rx;
@@ -80,10 +80,12 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
uint16_t nb_used;
uint16_t tx_id;
uint16_t sw_id;
+ uint64_t bytes;
sw_ring = txq->sw_ring;
txr = txq->tx_ring;
+ bytes = 0;
mask = txq->nb_tx_desc - 1;
sw_mask = txq->sw_size - 1;
tx_id = txq->tx_tail;
@@ -118,6 +120,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
tx_id = (tx_id + 1) & mask;
sw_id = (sw_id + 1) & sw_mask;
+ bytes += tx_pkt->pkt_len;
tx_pkt = tx_pkt->next;
} while (tx_pkt);
@@ -141,6 +144,9 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
rte_write32(tx_id, txq->qtx_tail);
txq->tx_tail = tx_id;
txq->sw_tail = sw_id;
+
+ txq->packets += nb_tx;
+ txq->bytes += bytes;
}
return nb_tx;