diff mbox series

[v1,9/9] baseband/acc: remove printf from PMD function

Message ID 20230209221929.265059-10-nicolas.chautru@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Maxime Coquelin
Headers
Series baseband/acc: VRB PMD fixes |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-unit-testing success Testing PASS
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ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-abi-testing success Testing PASS

Commit Message

Chautru, Nicolas Feb. 9, 2023, 10:19 p.m. UTC 
  Replacing usage of printf in companion function for
bbdev-test by rte_log.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/acc/rte_acc100_pmd.c | 18 +++++++++---------
 drivers/baseband/acc/rte_vrb_pmd.c    |  2 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

Comments

Maxime Coquelin Feb. 10, 2023, 9:45 a.m. UTC | #1 
On 2/9/23 23:19, Nicolas Chautru wrote:
> Replacing usage of printf in companion function for
> bbdev-test by rte_log.

I think it could be backported. If you agree please add Fixes tag and Cc
stable.

> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
>   drivers/baseband/acc/rte_acc100_pmd.c | 18 +++++++++---------
>   drivers/baseband/acc/rte_vrb_pmd.c    |  2 +-
>   2 files changed, 10 insertions(+), 10 deletions(-)

For the patch itself:
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

Thanks,
Maxime


> diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
> index 36f6fec5ad..40b5eaf089 100644
> --- a/drivers/baseband/acc/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc/rte_acc100_pmd.c
> @@ -4347,7 +4347,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
>   {
>   	int i, template_idx, qg_idx;
>   	uint32_t address, status, value;
> -	printf("Need to clear power-on 5GUL status in internal memory\n");
> +	rte_bbdev_log(WARNING, "Need to clear power-on 5GUL status in internal memory");
>   	/* Reset LDPC Cores */
>   	for (i = 0; i < ACC100_ENGINES_MAX; i++)
>   		acc_reg_write(d, HWPfFecUl5gCntrlReg +
> @@ -4421,7 +4421,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
>   	/* Force each engine which is in unspecified state */
>   	for (i = 0; i < num_failed_engine; i++) {
>   		int failed_engine = engines_to_restart[i];
> -		printf("Force engine %d\n", failed_engine);
> +		rte_bbdev_log(WARNING, "Force engine %d", failed_engine);
>   		for (template_idx = ACC100_SIG_UL_5G;
>   				template_idx <= ACC100_SIG_UL_5G_LAST;
>   				template_idx++) {
> @@ -4450,7 +4450,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
>   		acc_reg_write(d, HWPfQmgrIngressAq + 0x100, enq_req.val);
>   		usleep(ACC_LONG_WAIT * 100);
>   		if (desc->req.word0 != 2)
> -			printf("DMA Response %#"PRIx32"\n", desc->req.word0);
> +			rte_bbdev_log(WARNING, "DMA Response %#"PRIx32"\n", desc->req.word0);
>   	}
>   
>   	/* Reset LDPC Cores */
> @@ -4482,7 +4482,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
>   		} else
>   			acc_reg_write(d, address, 0);
>   	}
> -	printf("Number of 5GUL engines %d\n", numEngines);
> +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
>   
>   	rte_free(d->sw_rings_base);
>   	usleep(ACC_LONG_WAIT);
> @@ -4671,7 +4671,7 @@ acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
>   		} else
>   			acc_reg_write(d, address, 0);
>   	}
> -	printf("Number of 5GUL engines %d\n", numEngines);
> +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
>   	/* 4GDL */
>   	numQqsAcc += numQgs;
>   	numQgs	= conf->q_dl_4g.num_qgroups;
> @@ -4801,7 +4801,7 @@ acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
>   		version += acc_reg_read(d,
>   				HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
>   	if (version != ACC100_PRQ_DDR_VER) {
> -		printf("* Note: Not on DDR PRQ version %8x != %08x\n",
> +		rte_bbdev_log(ERR, "* Note: Not on DDR PRQ version %8x != %08x",
>   				version, ACC100_PRQ_DDR_VER);
>   	} else if (firstCfg) {
>   		/* ---- DDR configuration at boot up --- */
> @@ -4871,7 +4871,7 @@ acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
>   			if (value & 1)
>   				break;
>   		}
> -		printf("DDR Training completed in %d ms", i);
> +		rte_bbdev_log(INFO, "DDR Training completed in %d ms", i);
>   		/* Enable Memory Controller */
>   		acc_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
>   		/* Release AXI interface reset */
> @@ -5047,7 +5047,7 @@ acc101_configure(const char *dev_name, struct rte_acc_conf *conf)
>   		} else
>   			acc_reg_write(d, address, 0);
>   	}
> -	printf("Number of 5GUL engines %d\n", numEngines);
> +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
>   	/* 4GDL */
>   	numQqsAcc += numQgs;
>   	numQgs	= conf->q_dl_4g.num_qgroups;
> @@ -5185,7 +5185,7 @@ rte_acc_configure(const char *dev_name, struct rte_acc_conf *conf)
>   		return -ENODEV;
>   	}
>   	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
> -	printf("Configure dev id %x\n", pci_dev->id.device_id);
> +	rte_bbdev_log(INFO, "Configure dev id %x", pci_dev->id.device_id);
>   	if (pci_dev->id.device_id == ACC100_PF_DEVICE_ID)
>   		return acc100_configure(dev_name, conf);
>   	else if (pci_dev->id.device_id == ACC101_PF_DEVICE_ID)
> diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c
> index 18b5dab25f..c37f725415 100644
> --- a/drivers/baseband/acc/rte_vrb_pmd.c
> +++ b/drivers/baseband/acc/rte_vrb_pmd.c
> @@ -3633,7 +3633,7 @@ vrb1_configure(const char *dev_name, struct rte_acc_conf *conf)
>   		} else
>   			acc_reg_write(d, address, 0);
>   	}
> -	printf("Number of 5GUL engines %d\n", numEngines);
> +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
>   	/* 4GDL */
>   	numQqsAcc += numQgs;
>   	numQgs	= conf->q_dl_4g.num_qgroups;
Chautru, Nicolas Feb. 10, 2023, 5:46 p.m. UTC | #2 
Hi Maxime, 

> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Friday, February 10, 2023 1:45 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org
> Cc: Vargas, Hernan <hernan.vargas@intel.com>
> Subject: Re: [PATCH v1 9/9] baseband/acc: remove printf from PMD function
> 
> 
> 
> On 2/9/23 23:19, Nicolas Chautru wrote:
> > Replacing usage of printf in companion function for bbdev-test by
> > rte_log.
> 
> I think it could be backported. If you agree please add Fixes tag and Cc stable.

That function is only used for bbdev-test so would not really fix anything. 
We are changing this mainly to help imposing a rule moving forward for no printf in that PMD directory.
Based on this I don’t think we have to backport. But if you are convinced this is required, ok as well. 

> 
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> >   drivers/baseband/acc/rte_acc100_pmd.c | 18 +++++++++---------
> >   drivers/baseband/acc/rte_vrb_pmd.c    |  2 +-
> >   2 files changed, 10 insertions(+), 10 deletions(-)
> 
> For the patch itself:
> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
> 
> Thanks,
> Maxime
> 
> 
> > diff --git a/drivers/baseband/acc/rte_acc100_pmd.c
> > b/drivers/baseband/acc/rte_acc100_pmd.c
> > index 36f6fec5ad..40b5eaf089 100644
> > --- a/drivers/baseband/acc/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc/rte_acc100_pmd.c
> > @@ -4347,7 +4347,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct
> acc_device *d,
> >   {
> >   	int i, template_idx, qg_idx;
> >   	uint32_t address, status, value;
> > -	printf("Need to clear power-on 5GUL status in internal memory\n");
> > +	rte_bbdev_log(WARNING, "Need to clear power-on 5GUL status in
> > +internal memory");
> >   	/* Reset LDPC Cores */
> >   	for (i = 0; i < ACC100_ENGINES_MAX; i++)
> >   		acc_reg_write(d, HWPfFecUl5gCntrlReg + @@ -4421,7
> +4421,7 @@
> > poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
> >   	/* Force each engine which is in unspecified state */
> >   	for (i = 0; i < num_failed_engine; i++) {
> >   		int failed_engine = engines_to_restart[i];
> > -		printf("Force engine %d\n", failed_engine);
> > +		rte_bbdev_log(WARNING, "Force engine %d", failed_engine);
> >   		for (template_idx = ACC100_SIG_UL_5G;
> >   				template_idx <= ACC100_SIG_UL_5G_LAST;
> >   				template_idx++) {
> > @@ -4450,7 +4450,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct
> acc_device *d,
> >   		acc_reg_write(d, HWPfQmgrIngressAq + 0x100, enq_req.val);
> >   		usleep(ACC_LONG_WAIT * 100);
> >   		if (desc->req.word0 != 2)
> > -			printf("DMA Response %#"PRIx32"\n", desc-
> >req.word0);
> > +			rte_bbdev_log(WARNING, "DMA Response
> %#"PRIx32"\n",
> > +desc->req.word0);
> >   	}
> >
> >   	/* Reset LDPC Cores */
> > @@ -4482,7 +4482,7 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct
> acc_device *d,
> >   		} else
> >   			acc_reg_write(d, address, 0);
> >   	}
> > -	printf("Number of 5GUL engines %d\n", numEngines);
> > +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
> >
> >   	rte_free(d->sw_rings_base);
> >   	usleep(ACC_LONG_WAIT);
> > @@ -4671,7 +4671,7 @@ acc100_configure(const char *dev_name, struct
> rte_acc_conf *conf)
> >   		} else
> >   			acc_reg_write(d, address, 0);
> >   	}
> > -	printf("Number of 5GUL engines %d\n", numEngines);
> > +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
> >   	/* 4GDL */
> >   	numQqsAcc += numQgs;
> >   	numQgs	= conf->q_dl_4g.num_qgroups;
> > @@ -4801,7 +4801,7 @@ acc100_configure(const char *dev_name, struct
> rte_acc_conf *conf)
> >   		version += acc_reg_read(d,
> >   				HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
> >   	if (version != ACC100_PRQ_DDR_VER) {
> > -		printf("* Note: Not on DDR PRQ version %8x != %08x\n",
> > +		rte_bbdev_log(ERR, "* Note: Not on DDR PRQ version %8x !=
> %08x",
> >   				version, ACC100_PRQ_DDR_VER);
> >   	} else if (firstCfg) {
> >   		/* ---- DDR configuration at boot up --- */ @@ -4871,7 +4871,7
> @@
> > acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
> >   			if (value & 1)
> >   				break;
> >   		}
> > -		printf("DDR Training completed in %d ms", i);
> > +		rte_bbdev_log(INFO, "DDR Training completed in %d ms", i);
> >   		/* Enable Memory Controller */
> >   		acc_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
> >   		/* Release AXI interface reset */
> > @@ -5047,7 +5047,7 @@ acc101_configure(const char *dev_name, struct
> rte_acc_conf *conf)
> >   		} else
> >   			acc_reg_write(d, address, 0);
> >   	}
> > -	printf("Number of 5GUL engines %d\n", numEngines);
> > +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
> >   	/* 4GDL */
> >   	numQqsAcc += numQgs;
> >   	numQgs	= conf->q_dl_4g.num_qgroups;
> > @@ -5185,7 +5185,7 @@ rte_acc_configure(const char *dev_name, struct
> rte_acc_conf *conf)
> >   		return -ENODEV;
> >   	}
> >   	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
> > -	printf("Configure dev id %x\n", pci_dev->id.device_id);
> > +	rte_bbdev_log(INFO, "Configure dev id %x", pci_dev->id.device_id);
> >   	if (pci_dev->id.device_id == ACC100_PF_DEVICE_ID)
> >   		return acc100_configure(dev_name, conf);
> >   	else if (pci_dev->id.device_id == ACC101_PF_DEVICE_ID) diff --git
> > a/drivers/baseband/acc/rte_vrb_pmd.c
> > b/drivers/baseband/acc/rte_vrb_pmd.c
> > index 18b5dab25f..c37f725415 100644
> > --- a/drivers/baseband/acc/rte_vrb_pmd.c
> > +++ b/drivers/baseband/acc/rte_vrb_pmd.c
> > @@ -3633,7 +3633,7 @@ vrb1_configure(const char *dev_name, struct
> rte_acc_conf *conf)
> >   		} else
> >   			acc_reg_write(d, address, 0);
> >   	}
> > -	printf("Number of 5GUL engines %d\n", numEngines);
> > +	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
> >   	/* 4GDL */
> >   	numQqsAcc += numQgs;
> >   	numQgs	= conf->q_dl_4g.num_qgroups;
diff mbox series

Patch

diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 36f6fec5ad..40b5eaf089 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -4347,7 +4347,7 @@  poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
 {
 	int i, template_idx, qg_idx;
 	uint32_t address, status, value;
-	printf("Need to clear power-on 5GUL status in internal memory\n");
+	rte_bbdev_log(WARNING, "Need to clear power-on 5GUL status in internal memory");
 	/* Reset LDPC Cores */
 	for (i = 0; i < ACC100_ENGINES_MAX; i++)
 		acc_reg_write(d, HWPfFecUl5gCntrlReg +
@@ -4421,7 +4421,7 @@  poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
 	/* Force each engine which is in unspecified state */
 	for (i = 0; i < num_failed_engine; i++) {
 		int failed_engine = engines_to_restart[i];
-		printf("Force engine %d\n", failed_engine);
+		rte_bbdev_log(WARNING, "Force engine %d", failed_engine);
 		for (template_idx = ACC100_SIG_UL_5G;
 				template_idx <= ACC100_SIG_UL_5G_LAST;
 				template_idx++) {
@@ -4450,7 +4450,7 @@  poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
 		acc_reg_write(d, HWPfQmgrIngressAq + 0x100, enq_req.val);
 		usleep(ACC_LONG_WAIT * 100);
 		if (desc->req.word0 != 2)
-			printf("DMA Response %#"PRIx32"\n", desc->req.word0);
+			rte_bbdev_log(WARNING, "DMA Response %#"PRIx32"\n", desc->req.word0);
 	}
 
 	/* Reset LDPC Cores */
@@ -4482,7 +4482,7 @@  poweron_cleanup(struct rte_bbdev *bbdev, struct acc_device *d,
 		} else
 			acc_reg_write(d, address, 0);
 	}
-	printf("Number of 5GUL engines %d\n", numEngines);
+	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
 
 	rte_free(d->sw_rings_base);
 	usleep(ACC_LONG_WAIT);
@@ -4671,7 +4671,7 @@  acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
 		} else
 			acc_reg_write(d, address, 0);
 	}
-	printf("Number of 5GUL engines %d\n", numEngines);
+	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
 	/* 4GDL */
 	numQqsAcc += numQgs;
 	numQgs	= conf->q_dl_4g.num_qgroups;
@@ -4801,7 +4801,7 @@  acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
 		version += acc_reg_read(d,
 				HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
 	if (version != ACC100_PRQ_DDR_VER) {
-		printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+		rte_bbdev_log(ERR, "* Note: Not on DDR PRQ version %8x != %08x",
 				version, ACC100_PRQ_DDR_VER);
 	} else if (firstCfg) {
 		/* ---- DDR configuration at boot up --- */
@@ -4871,7 +4871,7 @@  acc100_configure(const char *dev_name, struct rte_acc_conf *conf)
 			if (value & 1)
 				break;
 		}
-		printf("DDR Training completed in %d ms", i);
+		rte_bbdev_log(INFO, "DDR Training completed in %d ms", i);
 		/* Enable Memory Controller */
 		acc_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
 		/* Release AXI interface reset */
@@ -5047,7 +5047,7 @@  acc101_configure(const char *dev_name, struct rte_acc_conf *conf)
 		} else
 			acc_reg_write(d, address, 0);
 	}
-	printf("Number of 5GUL engines %d\n", numEngines);
+	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
 	/* 4GDL */
 	numQqsAcc += numQgs;
 	numQgs	= conf->q_dl_4g.num_qgroups;
@@ -5185,7 +5185,7 @@  rte_acc_configure(const char *dev_name, struct rte_acc_conf *conf)
 		return -ENODEV;
 	}
 	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
-	printf("Configure dev id %x\n", pci_dev->id.device_id);
+	rte_bbdev_log(INFO, "Configure dev id %x", pci_dev->id.device_id);
 	if (pci_dev->id.device_id == ACC100_PF_DEVICE_ID)
 		return acc100_configure(dev_name, conf);
 	else if (pci_dev->id.device_id == ACC101_PF_DEVICE_ID)
diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c
index 18b5dab25f..c37f725415 100644
--- a/drivers/baseband/acc/rte_vrb_pmd.c
+++ b/drivers/baseband/acc/rte_vrb_pmd.c
@@ -3633,7 +3633,7 @@  vrb1_configure(const char *dev_name, struct rte_acc_conf *conf)
 		} else
 			acc_reg_write(d, address, 0);
 	}
-	printf("Number of 5GUL engines %d\n", numEngines);
+	rte_bbdev_log(INFO, "Number of 5GUL engines %d", numEngines);
 	/* 4GDL */
 	numQqsAcc += numQgs;
 	numQgs	= conf->q_dl_4g.num_qgroups;