From patchwork Tue Feb 7 16:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Yalavarthi X-Patchwork-Id: 123321 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E20B241C30; Tue, 7 Feb 2023 17:07:54 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2B2942D38; Tue, 7 Feb 2023 17:07:31 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BC40C427E9 for ; Tue, 7 Feb 2023 17:07:26 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317EgVTg017206 for ; Tue, 7 Feb 2023 08:07:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=h+nuKyOStfUr7Wzp0+ID0qetCKzgh30YE4DUhFIe5g4=; b=kmvYBmCi6QWa97rXtwoPdNsR1iCD0AUW1uGSPndgurNu9Sja/UDz9pZ2dx4bqynLp3ek of7Ga1LbPtjLCqw1HRhPNGEhjgWi+NBINy87XIYUY7JSLrYv42UCQsnr1PXcAhw7OFJI ioquX78ZqNs79zy8PwEfD4rr9Zb9M86DuzBEwQkJMtra9qwkOxAmGiAM3vdFcy9tdQp3 sLQStx9fKdbB2xinrP6mBCx8i5UEwruDGDRARTAuqxDj2sGMmZwrMfdBRoejoTmJY+lj 8TAaxzZQnZ22iehMMfxDjJLd3jC1ZEyWl7nve4hAJhBQSx+xN/rm+9//2kZwQdRZ5PnW UA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nkdyrssx7-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:25 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:24 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:24 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id DDA223F7085; Tue, 7 Feb 2023 08:07:23 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 06/39] ml/cnxk: parse ML firmware path from device args Date: Tue, 7 Feb 2023 08:06:46 -0800 Message-ID: <20230207160719.1307-7-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: l7MV2Zyz97qf_SOrKyZeA7zBTV9crfs0 X-Proofpoint-GUID: l7MV2Zyz97qf_SOrKyZeA7zBTV9crfs0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled parsing ML firmware path for cn10k. Default path is set as "/lib/firmware/mlip-fw.bin", when args are not provided. Added internal structures for ML firmware. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.c | 71 ++++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_dev.h | 12 ++++++ drivers/ml/cnxk/meson.build | 2 +- 3 files changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index fd45226add..117cac43aa 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -4,6 +4,8 @@ #include #include +#include +#include #include #include #include @@ -13,9 +15,70 @@ #include "cn10k_ml_dev.h" #include "cn10k_ml_ops.h" +#define CN10K_ML_FW_PATH "fw_path" + +#define CN10K_ML_FW_PATH_DEFAULT "/lib/firmware/mlip-fw.bin" + +static const char *const valid_args[] = {CN10K_ML_FW_PATH, NULL}; + /* Dummy operations for ML device */ struct rte_ml_dev_ops ml_dev_dummy_ops = {0}; +static int +parse_string_arg(const char *key __rte_unused, const char *value, void *extra_args) +{ + if (value == NULL || extra_args == NULL) + return -EINVAL; + + *(char **)extra_args = strdup(value); + + if (!*(char **)extra_args) + return -ENOMEM; + + return 0; +} + +static int +cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mldev) +{ + struct rte_kvargs *kvlist = NULL; + bool fw_path_set = false; + char *fw_path = NULL; + int ret = 0; + + if (devargs == NULL) + goto check_args; + + kvlist = rte_kvargs_parse(devargs->args, valid_args); + if (kvlist == NULL) { + plt_err("Error parsing devargs\n"); + return -EINVAL; + } + + if (rte_kvargs_count(kvlist, CN10K_ML_FW_PATH) == 1) { + ret = rte_kvargs_process(kvlist, CN10K_ML_FW_PATH, &parse_string_arg, &fw_path); + if (ret < 0) { + plt_err("Error processing arguments, key = %s\n", CN10K_ML_FW_PATH); + ret = -EINVAL; + goto exit; + } + fw_path_set = true; + } + +check_args: + if (!fw_path_set) + mldev->fw.path = CN10K_ML_FW_PATH_DEFAULT; + else + mldev->fw.path = fw_path; + plt_info("ML: %s = %s", CN10K_ML_FW_PATH, mldev->fw.path); + +exit: + if (kvlist) + rte_kvargs_free(kvlist); + + return ret; +} + static int cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) { @@ -49,6 +112,12 @@ cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_de if (rte_eal_process_type() == RTE_PROC_PRIMARY) { mldev->roc.pci_dev = pci_dev; + ret = cn10k_mldev_parse_devargs(dev->device->devargs, mldev); + if (ret) { + plt_err("Failed to parse devargs ret = %d", ret); + goto pmd_destroy; + } + ret = roc_ml_dev_init(&mldev->roc); if (ret) { plt_err("Failed to initialize ML ROC, ret = %d", ret); @@ -122,3 +191,5 @@ static struct rte_pci_driver cn10k_mldev_pmd = { RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd); RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table); RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, "vfio-pci"); + +RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH "="); diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h index e7fb5fc2e2..5333566cff 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.h +++ b/drivers/ml/cnxk/cn10k_ml_dev.h @@ -43,6 +43,15 @@ enum cn10k_ml_dev_state { ML_CN10K_DEV_STATE_CLOSED }; +/* ML firmware structure */ +struct cn10k_ml_fw { + /* Device reference */ + struct cn10k_ml_dev *mldev; + + /* Firmware file path */ + const char *path; +}; + /* Device private data */ struct cn10k_ml_dev { /* Device ROC */ @@ -50,6 +59,9 @@ struct cn10k_ml_dev { /* Configuration state */ enum cn10k_ml_dev_state state; + + /* Firmware */ + struct cn10k_ml_fw fw; }; #endif /* _CN10K_ML_DEV_H_ */ diff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build index caed62a9f3..7dc8a29a80 100644 --- a/drivers/ml/cnxk/meson.build +++ b/drivers/ml/cnxk/meson.build @@ -17,7 +17,7 @@ sources = files( 'cn10k_ml_ops.c', ) -deps += ['mldev', 'common_cnxk'] +deps += ['mldev', 'common_cnxk', 'kvargs'] if get_option('buildtype').contains('debug') cflags += [ '-DCNXK_ML_DEV_DEBUG' ]