[v5,04/39] ml/cnxk: add driver support to get device info

Message ID 20230207160719.1307-5-syalavarthi@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series Implementation of ML CNXK driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Srikanth Yalavarthi Feb. 7, 2023, 4:06 p.m. UTC
  Added support to get the cn10k ML device information. This is a
driver implementation for the RTE function rte_ml_dev_info_get.
ML device on cn10k supports one queue-pair in lock-free mode and
does not support segmented input output data.

Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
 drivers/ml/cnxk/cn10k_ml_dev.h | 15 +++++++++++++++
 drivers/ml/cnxk/cn10k_ml_ops.c | 23 ++++++++++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletion(-)
  

Patch

diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h
index 833a09791a..13d26373e4 100644
--- a/drivers/ml/cnxk/cn10k_ml_dev.h
+++ b/drivers/ml/cnxk/cn10k_ml_dev.h
@@ -10,6 +10,21 @@ 
 /* Marvell OCTEON CN10K ML PMD device name */
 #define MLDEV_NAME_CN10K_PMD ml_cn10k
 
+/* Device alignment size */
+#define ML_CN10K_ALIGN_SIZE 128
+
+/* Maximum number of models per device */
+#define ML_CN10K_MAX_MODELS 16
+
+/* Maximum number of queue-pairs per device */
+#define ML_CN10K_MAX_QP_PER_DEVICE 1
+
+/* Maximum number of descriptors per queue-pair */
+#define ML_CN10K_MAX_DESC_PER_QP 1024
+
+/* Maximum number of segments for IO data */
+#define ML_CN10K_MAX_SEGMENTS 1
+
 /* Device private data */
 struct cn10k_ml_dev {
 	/* Device ROC */
diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c
index 39843e3ee5..bad5ad4713 100644
--- a/drivers/ml/cnxk/cn10k_ml_ops.c
+++ b/drivers/ml/cnxk/cn10k_ml_ops.c
@@ -5,6 +5,27 @@ 
 #include <rte_mldev.h>
 #include <rte_mldev_pmd.h>
 
+#include "cn10k_ml_dev.h"
 #include "cn10k_ml_ops.h"
 
-struct rte_ml_dev_ops cn10k_ml_ops = {0};
+static int
+cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)
+{
+	if (dev_info == NULL)
+		return -EINVAL;
+
+	memset(dev_info, 0, sizeof(struct rte_ml_dev_info));
+	dev_info->driver_name = dev->device->driver->name;
+	dev_info->max_models = ML_CN10K_MAX_MODELS;
+	dev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE;
+	dev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;
+	dev_info->max_segments = ML_CN10K_MAX_SEGMENTS;
+	dev_info->min_align_size = ML_CN10K_ALIGN_SIZE;
+
+	return 0;
+}
+
+struct rte_ml_dev_ops cn10k_ml_ops = {
+	/* Device control ops */
+	.dev_info_get = cn10k_ml_dev_info_get,
+};