From patchwork Tue Feb 7 16:07:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Yalavarthi X-Patchwork-Id: 123354 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A420741C30; Tue, 7 Feb 2023 17:12:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA39B43008; Tue, 7 Feb 2023 17:08:08 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D5D8A42D5D for ; Tue, 7 Feb 2023 17:07:38 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317BL2vw005847 for ; Tue, 7 Feb 2023 08:07:38 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=lP+8w4lJ4bygBYRZC8TUAnKIerEvl+BRypJgebjxcsU=; b=WJE8NyQDS1CGm7X8tBVZNJihKA50DAqiz9DBpgoXfQVpWPsLGPwkD96SZNTv8D8acl9v BzF86VbstxbqUAgBhZwEA0QMqW0bIAX4p5Roqvho4iSr9b2p31iRtE7SCDnAZOWNTbYg 3wzVD2zYu/mwzjFbsmc+uM7tU4R7bnWbEq+omIn4iOpH5+Urr9pLtcX082eFP1HPVjl8 2OxZlFZJL5lpVB+0miqcKQ344TeKd/TFTar4lOMR5TGpcZpX6XDGXoYSR7f8S5YhUIn0 MuzYoGd3hOC+K/bcoPhVT9OOzmBETTR/9JvGro1kzt+uHwVK8A3GJegGfbEu+OOcKBKd qg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nhqrtmsnd-18 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:38 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:31 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:31 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 8D1E23F7083; Tue, 7 Feb 2023 08:07:31 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 35/39] ml/cnxk: add support to select OCM allocation mode Date: Tue, 7 Feb 2023 08:07:15 -0800 Message-ID: <20230207160719.1307-36-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: FI4WldUEff0WPoTpUxuR_2jooOE-aAWF X-Proofpoint-ORIG-GUID: FI4WldUEff0WPoTpUxuR_2jooOE-aAWF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added device argument "ocm_alloc_mode" to select OCM allocation method during model start. Two modes are supported by the driver. Added implementation for ocm_alloc_mode lowest as default. ocm_alloc_mode: lowest: Allocate from first available free slot / lowest tile ID in OCM (default) largest: Allocate from a slot with maximum free memory Signed-off-by: Srikanth Yalavarthi Acked-by: Prince Takkar --- drivers/ml/cnxk/cn10k_ml_dev.c | 45 +++++++++++++++++++++++++++++----- drivers/ml/cnxk/cn10k_ml_ocm.c | 6 ++--- drivers/ml/cnxk/cn10k_ml_ocm.h | 3 +++ 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index 948708a420..5c02d67c8e 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -21,11 +21,13 @@ #define CN10K_ML_FW_ENABLE_DPE_WARNINGS "enable_dpe_warnings" #define CN10K_ML_FW_REPORT_DPE_WARNINGS "report_dpe_warnings" #define CN10K_ML_DEV_CACHE_MODEL_DATA "cache_model_data" +#define CN10K_ML_OCM_ALLOC_MODE "ocm_alloc_mode" #define CN10K_ML_FW_PATH_DEFAULT "/lib/firmware/mlip-fw.bin" #define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1 #define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0 #define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT 1 +#define CN10K_ML_OCM_ALLOC_MODE_DEFAULT "lowest" /* ML firmware macros */ #define FW_MEMZONE_NAME "ml_cn10k_fw_mz" @@ -39,9 +41,12 @@ #define FW_ENABLE_DPE_WARNING_BITMASK BIT(0) #define FW_REPORT_DPE_WARNING_BITMASK BIT(1) -static const char *const valid_args[] = {CN10K_ML_FW_PATH, CN10K_ML_FW_ENABLE_DPE_WARNINGS, +static const char *const valid_args[] = {CN10K_ML_FW_PATH, + CN10K_ML_FW_ENABLE_DPE_WARNINGS, CN10K_ML_FW_REPORT_DPE_WARNINGS, - CN10K_ML_DEV_CACHE_MODEL_DATA, NULL}; + CN10K_ML_DEV_CACHE_MODEL_DATA, + CN10K_ML_OCM_ALLOC_MODE, + NULL}; /* Dummy operations for ML device */ struct rte_ml_dev_ops ml_dev_dummy_ops = {0}; @@ -81,6 +86,8 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde bool report_dpe_warnings_set = false; bool cache_model_data_set = false; struct rte_kvargs *kvlist = NULL; + bool ocm_alloc_mode_set = false; + char *ocm_alloc_mode = NULL; bool fw_path_set = false; char *fw_path = NULL; int ret = 0; @@ -140,6 +147,17 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde cache_model_data_set = true; } + if (rte_kvargs_count(kvlist, CN10K_ML_OCM_ALLOC_MODE) == 1) { + ret = rte_kvargs_process(kvlist, CN10K_ML_OCM_ALLOC_MODE, &parse_string_arg, + &ocm_alloc_mode); + if (ret < 0) { + plt_err("Error processing arguments, key = %s\n", CN10K_ML_OCM_ALLOC_MODE); + ret = -EINVAL; + goto exit; + } + ocm_alloc_mode_set = true; + } + check_args: if (!fw_path_set) mldev->fw.path = CN10K_ML_FW_PATH_DEFAULT; @@ -183,6 +201,20 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde } plt_info("ML: %s = %d", CN10K_ML_DEV_CACHE_MODEL_DATA, mldev->cache_model_data); + if (!ocm_alloc_mode_set) { + mldev->ocm.alloc_mode = CN10K_ML_OCM_ALLOC_MODE_DEFAULT; + } else { + if (!((strcmp(ocm_alloc_mode, "lowest") == 0) || + (strcmp(ocm_alloc_mode, "largest") == 0))) { + plt_err("Invalid argument, %s = %s\n", CN10K_ML_OCM_ALLOC_MODE, + ocm_alloc_mode); + ret = -EINVAL; + goto exit; + } + mldev->ocm.alloc_mode = ocm_alloc_mode; + } + plt_info("ML: %s = %s", CN10K_ML_OCM_ALLOC_MODE, mldev->ocm.alloc_mode); + exit: if (kvlist) rte_kvargs_free(kvlist); @@ -720,7 +752,8 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd); RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table); RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, "vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, - CN10K_ML_FW_PATH "=" CN10K_ML_FW_ENABLE_DPE_WARNINGS - "=<0|1>" CN10K_ML_FW_REPORT_DPE_WARNINGS - "=<0|1>" CN10K_ML_DEV_CACHE_MODEL_DATA "=<0|1>"); +RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH + "=" CN10K_ML_FW_ENABLE_DPE_WARNINGS + "=<0|1>" CN10K_ML_FW_REPORT_DPE_WARNINGS + "=<0|1>" CN10K_ML_DEV_CACHE_MODEL_DATA + "=<0|1>" CN10K_ML_OCM_ALLOC_MODE "="); diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c index 0b04fcc2da..551faef7eb 100644 --- a/drivers/ml/cnxk/cn10k_ml_ocm.c +++ b/drivers/ml/cnxk/cn10k_ml_ocm.c @@ -230,7 +230,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w int wb_page_start_curr; int max_slot_sz_curr; uint8_t tile_start; - int ocm_alloc_mode; int wb_page_start; uint16_t tile_id; uint16_t word_id; @@ -255,7 +254,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w max_slot_sz_curr = 0; max_slot_sz = 0; tile_idx = 0; - ocm_alloc_mode = 2; if ((start_tile != -1) && (start_tile % num_tiles != 0)) { plt_err("Invalid start_tile, %d", start_tile); @@ -303,13 +301,13 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w } } - if (ocm_alloc_mode == 1) { + if (strcmp(ocm->alloc_mode, "lowest") == 0) { wb_page_start = slot_index_lowest(local_ocm_mask, ocm->mask_words, wb_pages, 0); if (wb_page_start != -1) { /* Have a valid slot for WB, else next set of tiles */ tile_idx = tile_start; goto found; } - } else if (ocm_alloc_mode == 2) { + } else if (strcmp(ocm->alloc_mode, "largest") == 0) { wb_page_start_curr = slot_index_largest(local_ocm_mask, ocm->mask_words, wb_pages, &max_slot_sz_curr); if (max_slot_sz_curr > max_slot_sz) { diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h index 0c7172a671..5f018b410a 100644 --- a/drivers/ml/cnxk/cn10k_ml_ocm.h +++ b/drivers/ml/cnxk/cn10k_ml_ocm.h @@ -58,6 +58,9 @@ struct cn10k_ml_ocm { /* OCM spinlock, used to update OCM state */ rte_spinlock_t lock; + /* OCM allocation mode */ + const char *alloc_mode; + /* Number of OCM tiles */ uint8_t num_tiles;