From patchwork Tue Feb 7 16:07:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Yalavarthi X-Patchwork-Id: 123352 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 795B741C30; Tue, 7 Feb 2023 17:11:59 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC39F42FF2; Tue, 7 Feb 2023 17:08:06 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8504342D52 for ; Tue, 7 Feb 2023 17:07:37 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317BL2vu005847 for ; Tue, 7 Feb 2023 08:07:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bQid8g7/TgRhAVCXeUZsdULRHG2l4aU4Wt668oxEs5I=; b=LWKjMH/i7Yq9B/qMpJ/46SzGV/8VFOOwyBirTgLUU/BzCHknR8xth/A1T8BzN+/SU6V3 XnkH30wDL0MS6QGD+/IRrz34Z6cLrMTZFNhRqlzPmfw2JkkxA1rqiXXGeWLgd07Qp/sg Pnf2RZ3kf+u4UoquKJYVhgi3TKQ/v9gyZvILrvVN2UCQ91nPGgcpsRkggcJz03LoUCLo R0yZuNpIp/AiOzdSs4fxEgwmlliIS50YSnGZ8ziKT3CM9cnko5zRxfPhfv1E0X5j2vrK QZRWV94cEiUgsFnbVA/pKoY2yoU3wGLyqDeL9rB/onN1NRpti1rx+fYuGdLYZK4H0+2b jA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nhqrtmsnd-16 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:36 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:31 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:31 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 066F73F7085; Tue, 7 Feb 2023 08:07:31 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 33/39] ml/cnxk: add support to report DPE FW warnings Date: Tue, 7 Feb 2023 08:07:13 -0800 Message-ID: <20230207160719.1307-34-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: yZOuN_2h4BpQ50s6Dmzhlcyq56_ooy46 X-Proofpoint-ORIG-GUID: yZOuN_2h4BpQ50s6Dmzhlcyq56_ooy46 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled support to enable and report DPE warnings from ML firmware. Configure firmware load flags based on the device arguments. Default values: enable_dpe_errors = 1 report_dpe_errors = 0 Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.c | 94 +++++++++++++++++++++++++++++++--- drivers/ml/cnxk/cn10k_ml_dev.h | 6 +++ 2 files changed, 93 insertions(+), 7 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index 76ed853a3c..ac6592891b 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -17,9 +17,13 @@ #include "cn10k_ml_dev.h" #include "cn10k_ml_ops.h" -#define CN10K_ML_FW_PATH "fw_path" +#define CN10K_ML_FW_PATH "fw_path" +#define CN10K_ML_FW_ENABLE_DPE_WARNINGS "enable_dpe_warnings" +#define CN10K_ML_FW_REPORT_DPE_WARNINGS "report_dpe_warnings" -#define CN10K_ML_FW_PATH_DEFAULT "/lib/firmware/mlip-fw.bin" +#define CN10K_ML_FW_PATH_DEFAULT "/lib/firmware/mlip-fw.bin" +#define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1 +#define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0 /* ML firmware macros */ #define FW_MEMZONE_NAME "ml_cn10k_fw_mz" @@ -28,9 +32,13 @@ #define FW_EXCEPTION_BUFFER_SIZE 0x400 #define FW_LINKER_OFFSET 0x80000 #define FW_WAIT_CYCLES 100 -#define FW_LOAD_FLAGS 0x1 -static const char *const valid_args[] = {CN10K_ML_FW_PATH, NULL}; +/* Firmware flags */ +#define FW_ENABLE_DPE_WARNING_BITMASK BIT(0) +#define FW_REPORT_DPE_WARNING_BITMASK BIT(1) + +static const char *const valid_args[] = {CN10K_ML_FW_PATH, CN10K_ML_FW_ENABLE_DPE_WARNINGS, + CN10K_ML_FW_REPORT_DPE_WARNINGS, NULL}; /* Dummy operations for ML device */ struct rte_ml_dev_ops ml_dev_dummy_ops = {0}; @@ -49,9 +57,25 @@ parse_string_arg(const char *key __rte_unused, const char *value, void *extra_ar return 0; } +static int +parse_integer_arg(const char *key __rte_unused, const char *value, void *extra_args) +{ + int *i = (int *)extra_args; + + *i = atoi(value); + if (*i < 0) { + plt_err("Argument has to be positive."); + return -EINVAL; + } + + return 0; +} + static int cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mldev) { + bool enable_dpe_warnings_set = false; + bool report_dpe_warnings_set = false; struct rte_kvargs *kvlist = NULL; bool fw_path_set = false; char *fw_path = NULL; @@ -76,6 +100,30 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde fw_path_set = true; } + if (rte_kvargs_count(kvlist, CN10K_ML_FW_ENABLE_DPE_WARNINGS) == 1) { + ret = rte_kvargs_process(kvlist, CN10K_ML_FW_ENABLE_DPE_WARNINGS, + &parse_integer_arg, &mldev->fw.enable_dpe_warnings); + if (ret < 0) { + plt_err("Error processing arguments, key = %s\n", + CN10K_ML_FW_ENABLE_DPE_WARNINGS); + ret = -EINVAL; + goto exit; + } + enable_dpe_warnings_set = true; + } + + if (rte_kvargs_count(kvlist, CN10K_ML_FW_REPORT_DPE_WARNINGS) == 1) { + ret = rte_kvargs_process(kvlist, CN10K_ML_FW_REPORT_DPE_WARNINGS, + &parse_integer_arg, &mldev->fw.report_dpe_warnings); + if (ret < 0) { + plt_err("Error processing arguments, key = %s\n", + CN10K_ML_FW_REPORT_DPE_WARNINGS); + ret = -EINVAL; + goto exit; + } + report_dpe_warnings_set = true; + } + check_args: if (!fw_path_set) mldev->fw.path = CN10K_ML_FW_PATH_DEFAULT; @@ -83,6 +131,30 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde mldev->fw.path = fw_path; plt_info("ML: %s = %s", CN10K_ML_FW_PATH, mldev->fw.path); + if (!enable_dpe_warnings_set) { + mldev->fw.enable_dpe_warnings = CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT; + } else { + if ((mldev->fw.enable_dpe_warnings < 0) || (mldev->fw.enable_dpe_warnings > 1)) { + plt_err("Invalid argument, %s = %d\n", CN10K_ML_FW_ENABLE_DPE_WARNINGS, + mldev->fw.enable_dpe_warnings); + ret = -EINVAL; + goto exit; + } + } + plt_info("ML: %s = %d", CN10K_ML_FW_ENABLE_DPE_WARNINGS, mldev->fw.enable_dpe_warnings); + + if (!report_dpe_warnings_set) { + mldev->fw.report_dpe_warnings = CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT; + } else { + if ((mldev->fw.report_dpe_warnings < 0) || (mldev->fw.report_dpe_warnings > 1)) { + plt_err("Invalid argument, %s = %d\n", CN10K_ML_FW_REPORT_DPE_WARNINGS, + mldev->fw.report_dpe_warnings); + ret = -EINVAL; + goto exit; + } + } + plt_info("ML: %s = %d", CN10K_ML_FW_REPORT_DPE_WARNINGS, mldev->fw.report_dpe_warnings); + exit: if (kvlist) rte_kvargs_free(kvlist); @@ -208,9 +280,15 @@ cn10k_ml_fw_print_info(struct cn10k_ml_fw *fw) uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw) { - PLT_SET_USED(fw); + uint64_t flags = 0x0; + + if (fw->enable_dpe_warnings) + flags = flags | FW_ENABLE_DPE_WARNING_BITMASK; + + if (fw->report_dpe_warnings) + flags = flags | FW_REPORT_DPE_WARNING_BITMASK; - return FW_LOAD_FLAGS; + return flags; } static int @@ -614,4 +692,6 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd); RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table); RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, "vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH "="); +RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, + CN10K_ML_FW_PATH "=" CN10K_ML_FW_ENABLE_DPE_WARNINGS + "=<0|1>" CN10K_ML_FW_REPORT_DPE_WARNINGS "=<0|1>"); diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h index b7ff369ba8..9ba56ffba6 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.h +++ b/drivers/ml/cnxk/cn10k_ml_dev.h @@ -349,6 +349,12 @@ struct cn10k_ml_fw { /* Firmware file path */ const char *path; + /* Enable DPE warnings */ + int enable_dpe_warnings; + + /* Report DPE warnings */ + int report_dpe_warnings; + /* Data buffer */ uint8_t *data;