diff mbox series

[v5,28/39] ml/cnxk: add internal function for sync mode run

Message ID 20230207160719.1307-29-syalavarthi@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series Implementation of ML CNXK driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Srikanth Yalavarthi Feb. 7, 2023, 4:07 p.m. UTC 
  Added internal function to execute ML inference requests
in synchronous mode. Sync mode inference execution is used
to launch inference requests without using a queue-pair.

Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
 drivers/ml/cnxk/cn10k_ml_ops.c | 53 ++++++++++++++++++++++++++++++++++
 drivers/ml/cnxk/cn10k_ml_ops.h |  1 +
 2 files changed, 54 insertions(+)

Comments

Prince Takkar Feb. 27, 2023, 10:42 a.m. UTC | #1 
> -----Original Message-----
> From: Srikanth Yalavarthi <syalavarthi@marvell.com>
> Sent: Tuesday, February 7, 2023 9:37 PM
> To: Srikanth Yalavarthi <syalavarthi@marvell.com>
> Cc: dev@dpdk.org; Shivah Shankar Shankar Narayan Rao
> <sshankarnara@marvell.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>;
> Anup Prabhu <aprabhu@marvell.com>; Prince Takkar <ptakkar@marvell.com>;
> Parijat Shukla <pshukla@marvell.com>
> Subject: [PATCH v5 28/39] ml/cnxk: add internal function for sync mode run
> 
> Added internal function to execute ML inference requests in synchronous mode.
> Sync mode inference execution is used to launch inference requests without
> using a queue-pair.
> 
> Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
> ---
>  drivers/ml/cnxk/cn10k_ml_ops.c | 53 ++++++++++++++++++++++++++++++++++
>  drivers/ml/cnxk/cn10k_ml_ops.h |  1 +
>  2 files changed, 54 insertions(+)
> 
Acked-by: Prince Takkar <ptakkar@marvell.com>
diff mbox series

Patch

diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c
index 51f1c92a8d..87778c37bb 100644
--- a/drivers/ml/cnxk/cn10k_ml_ops.c
+++ b/drivers/ml/cnxk/cn10k_ml_ops.c
@@ -1533,6 +1533,59 @@  cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op
 	return count;
 }
 
+__rte_hot int
+cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)
+{
+	struct cn10k_ml_model *model;
+	struct cn10k_ml_dev *mldev;
+	struct cn10k_ml_req *req;
+	bool timeout;
+	int ret = 0;
+
+	mldev = dev->data->dev_private;
+	model = dev->data->models[op->model_id];
+	req = model->req;
+
+	cn10k_ml_prep_fp_job_descriptor(dev, req, op);
+
+	memset(&req->result, 0, sizeof(struct cn10k_ml_result));
+	req->result.user_ptr = op->user_ptr;
+
+	plt_write64(ML_CN10K_POLL_JOB_START, &req->status);
+	req->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd);
+
+	timeout = true;
+	req->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz();
+	do {
+		if (roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd)) {
+			req->op = op;
+			timeout = false;
+			break;
+		}
+	} while (plt_tsc_cycles() < req->timeout);
+
+	if (timeout) {
+		ret = -EBUSY;
+		goto error_enqueue;
+	}
+
+	timeout = true;
+	do {
+		if (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) {
+			timeout = false;
+			break;
+		}
+	} while (plt_tsc_cycles() < req->timeout);
+
+	if (timeout)
+		ret = -ETIME;
+	else
+		cn10k_ml_result_update(dev, -1, &req->result, req->op);
+
+error_enqueue:
+	return ret;
+}
+
 struct rte_ml_dev_ops cn10k_ml_ops = {
 	/* Device control ops */
 	.dev_info_get = cn10k_ml_dev_info_get,
diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h
index f6aab4a609..7c35bf7539 100644
--- a/drivers/ml/cnxk/cn10k_ml_ops.h
+++ b/drivers/ml/cnxk/cn10k_ml_ops.h
@@ -75,5 +75,6 @@  __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id
 					  struct rte_ml_op **ops, uint16_t nb_ops);
 __rte_hot uint16_t cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id,
 					  struct rte_ml_op **ops, uint16_t nb_ops);
+__rte_hot int cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op);
 
 #endif /* _CN10K_ML_OPS_H_ */