From patchwork Tue Feb 7 16:06:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Yalavarthi X-Patchwork-Id: 123326 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F33AC41C30; Tue, 7 Feb 2023 17:08:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8931D42D53; Tue, 7 Feb 2023 17:07:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 435C642C54 for ; Tue, 7 Feb 2023 17:07:28 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317EgVTj017206 for ; Tue, 7 Feb 2023 08:07:27 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=JG6jXO4k0Prwv+SBur/RV9/8mZnzG5/3LyHHY9iJ7vc=; b=RC9tR7gOFQiawKicEUq1iWPtnPQhcdIfp/+VcLOeCqu2umzC+IvqL+RvZXas9O0feD0K h1Dgh5jmlOKfioZN8dJzICXFij5nBvS6qpsd8FbRadi+vaSaoe7Kqh7t+P1x6bJYFKug 7bTnBFn+0APTWs3VZlbo7mw0NEzrVV/pJkZQLA6PQYR05u8UFj3iw4T3O6aVHJpWcWu5 5BUTPP9seSaQxYQMFWPK2FMrG2UCxaSX9mBH2860OkQdMocDbAPG8vOQFHVIETvik7MT pbGJS0d1VVHNbb9EP1eip7dL1m8ZhU7ajY6BFYlKO7iphdHzoHjsWY/lD571OMPLAVwf 2A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nkdyrssx7-6 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:27 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:24 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:24 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id A5D423F7083; Tue, 7 Feb 2023 08:07:24 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 09/39] ml/cnxk: enable support for device start and stop Date: Tue, 7 Feb 2023 08:06:49 -0800 Message-ID: <20230207160719.1307-10-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: l8n0GYCAGvr77JF5AEhVgrI7uBgRtni2 X-Proofpoint-GUID: l8n0GYCAGvr77JF5AEhVgrI7uBgRtni2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implemented ML driver functions to start and stop ML device. Start / Stop would enable or disable ML device to accept inference requests. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 42 +++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 3df1254dca..a9f14fe4c5 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -104,9 +104,45 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev) return rte_dev_remove(dev->device); } +static int +cn10k_ml_dev_start(struct rte_ml_dev *dev) +{ + struct cn10k_ml_dev *mldev; + uint64_t reg_val64; + + mldev = dev->data->dev_private; + + reg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG); + reg_val64 |= ROC_ML_CFG_ENA; + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + plt_ml_dbg("ML_CFG => 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_CFG)); + + mldev->state = ML_CN10K_DEV_STATE_STARTED; + + return 0; +} + +static int +cn10k_ml_dev_stop(struct rte_ml_dev *dev) +{ + struct cn10k_ml_dev *mldev; + uint64_t reg_val64; + + mldev = dev->data->dev_private; + + reg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG); + reg_val64 &= ~ROC_ML_CFG_ENA; + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + plt_ml_dbg("ML_CFG => 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_CFG)); + + mldev->state = ML_CN10K_DEV_STATE_CONFIGURED; + + return 0; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ - .dev_info_get = cn10k_ml_dev_info_get, - .dev_configure = cn10k_ml_dev_configure, - .dev_close = cn10k_ml_dev_close, + .dev_info_get = cn10k_ml_dev_info_get, .dev_configure = cn10k_ml_dev_configure, + .dev_close = cn10k_ml_dev_close, .dev_start = cn10k_ml_dev_start, + .dev_stop = cn10k_ml_dev_stop, };