From patchwork Fri Feb 3 10:05:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 123013 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F37841BBB; Fri, 3 Feb 2023 11:06:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3494642D12; Fri, 3 Feb 2023 11:06:02 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 52DEB42D16 for ; Fri, 3 Feb 2023 11:06:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675418760; x=1706954760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eBfl7x4xOzUq7hjhXhCS2QinKqIKPFCkiUbnRWsIPtE=; b=hHAWe5yPAyjDXodzDrVBAJeR6WBUlvYH6yBdAUhmKiipzsgK19G8ga8I /5eiw090KUf4zVyu9eagxz3WKHGfbGmb/RQYrWKG7DisRMeQXqKgoj3nJ LzO5FC/1ZNil2F+EFw2AsFc5k1b7QOxWh8vz0G4UaO/FH3TXT71p5/EQ2 F+yrlMnTqQb+hpjunUGRQZnOpiKH9y1CuDxAxrQeqK+RC5YCJt5C8+RsQ 640mv6R3fAYqkdmry+/GU4lBPAepFtoE4X9+aAt/YgCeOkOUqJ1+91LSk m0sXIWMPNy93KykzRNrPxz6GFXDO0vzlGZM5SBhQoAaRYa+L9xuEMcMX2 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10609"; a="316705056" X-IronPort-AV: E=Sophos;i="5.97,270,1669104000"; d="scan'208";a="316705056" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2023 02:05:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10609"; a="994465499" X-IronPort-AV: E=Sophos;i="5.97,270,1669104000"; d="scan'208";a="994465499" Received: from silpixa00401385.ir.intel.com ([10.237.214.158]) by fmsmga005.fm.intel.com with ESMTP; 03 Feb 2023 02:05:58 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: jasvinder.singh@intel.com, Bruce Richardson , Cristian Dumitrescu Subject: [PATCH 3/4] examples/qos_sched: use bigger bursts on dequeue Date: Fri, 3 Feb 2023 10:05:32 +0000 Message-Id: <20230203100533.10377-4-bruce.richardson@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203100533.10377-1-bruce.richardson@intel.com> References: <20230203100533.10377-1-bruce.richardson@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org While performance of the QoS block drops sharply if the dequeue size is greater than or equal to the enqueue size, increasing the dequeue size to just under the enqueue one gives improved performance when the scheduler is not keeping up with the line rate. Signed-off-by: Bruce Richardson Acked-by: Cristian Dumitrescu --- doc/guides/sample_app_ug/qos_scheduler.rst | 2 +- examples/qos_sched/main.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.37.2 diff --git a/doc/guides/sample_app_ug/qos_scheduler.rst b/doc/guides/sample_app_ug/qos_scheduler.rst index f376554dd9..9936b99172 100644 --- a/doc/guides/sample_app_ug/qos_scheduler.rst +++ b/doc/guides/sample_app_ug/qos_scheduler.rst @@ -91,7 +91,7 @@ Optional application parameters include: * B = I/O RX lcore write burst size to the output software rings, worker lcore read burst size from input software rings,QoS enqueue size (the default value is 64) -* C = QoS dequeue size (the default value is 32) +* C = QoS dequeue size (the default value is 63) * D = Worker lcore write burst size to the NIC TX (the default value is 64) diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h index b9c301483a..d8f3e32c83 100644 --- a/examples/qos_sched/main.h +++ b/examples/qos_sched/main.h @@ -26,7 +26,7 @@ extern "C" { #define MAX_PKT_RX_BURST 64 #define PKT_ENQUEUE 64 -#define PKT_DEQUEUE 32 +#define PKT_DEQUEUE 63 #define MAX_PKT_TX_BURST 64 #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */