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Thu, 2 Feb 2023 08:25:57 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" Subject: [PATCH v2 7/8] common/mlx5: add LZ4 capabilities check Date: Thu, 2 Feb 2023 18:25:36 +0200 Message-ID: <20230202162537.1067595-8-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230202162537.1067595-1-michaelba@nvidia.com> References: <20230109075838.2508039-1-michaelba@nvidia.com> <20230202162537.1067595-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT078:EE_|CY5PR12MB6597:EE_ X-MS-Office365-Filtering-Correlation-Id: 44f3fb4c-22d0-4ad0-6f1a-08db053a2e40 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vp+rEJ1DA//+Vm95hLTsQrki2jvSz4Wy1bsTORakslm+cxP6AY1FrJ4bf4E18cmWI2wzntAQXZR+NziAWkJ/Tcn4SUeYTHmBOs8ZXcVmXWLuTGukFlVctsbz+SPSRBA8aD31LbVIRV34vB1teTCOpXIfXYx+fnRiFuHjkvcA3BlEt4NQ57KchZb2kPMOT5KSAMjD759wk1wNX7bX+4bOTzJwqH0kD2mazh1XiW7gfMQNBMujquQPLls6i0PIcqdWj1j9qYjZSSiynWrYPjSSS8SzhnYPkSZLHMY9YSnmwC9EalF+4bENx7AcX5mfqUMsb19uILs2qFCLQlszIJLiLoeBZGFr1YaSw/Kmu8cEDcAeji/EXy1EUSrNT2xWoPsVk5j68o0C3RU1UPbpfwPHSSxL8W5dzWXlxYHyqIfKJsbdGslL05vdTcLUV7IwSj5deY7oc3DF82931AILipoG32jDsMP5VD+WkIkGreAijC49eeowozvsLB9wE/YKael+0eT97elSWHsXsKi3ts0pbXSIKh3380/TuEqrU43sQHtSkZ1anCMCDV9N44nJ6CSesWEZM1qAavRC04RYt6H0yd3Po3NIn8FYMjbeEVZ+0QxhJ7oBsN8GR76kbQbWcj9tY4dx9JLBgptT4sOKnUSKca3MAQGj9O7flSS/KpDjcPtjiOMMyDooTyMu+nGscRp5kV9DtYlsQnK3xRstcgaU9w== X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Signed-off-by: Michael Baum --- drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index dfec4dcf1b..f30daa19c7 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -989,6 +989,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_compress_mmo_size); attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, log_decompress_mmo_size); + attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_data_only_v2); + attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_no_checksum_v2); + attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_checksum_v2); attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_flow_tag); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index edb387e272..a82af9426d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -267,6 +267,9 @@ struct mlx5_hca_attr { uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; uint32_t log_max_mmo_decompress:5; + uint32_t decomp_lz4_data_only_en:1; + uint32_t decomp_lz4_no_checksum_en:1; + uint32_t decomp_lz4_checksum_en:1; uint32_t umr_modify_entity_size_disabled:1; uint32_t umr_indirect_mkey_disabled:1; uint32_t log_min_stride_wqe_sz:5; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 377cbfab87..f89af8b96b 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -578,9 +578,19 @@ struct mlx5_rdma_write_wqe { #define MLX5_OPC_MOD_MMO_DECOMP 0x3u #define MLX5_OPC_MOD_MMO_DMA 0x1u +#define WQE_GGA_DECOMP_DEFLATE 0x0u +#define WQE_GGA_DECOMP_LZ4 0x2u + +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u + #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u +#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u +#define WQE_GGA_DECOMP_TYPE_OFFSET 8u +#define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u + #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u @@ -599,7 +609,7 @@ struct mlx5_gga_wqe { uint32_t opcode; uint32_t sq_ds; uint32_t flags; - uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ + uint32_t gga_ctrl1; uint32_t gga_ctrl2; uint32_t opaque_lkey; uint64_t opaque_vaddr; @@ -1434,7 +1444,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_dma_mmo_size[0x5]; u8 reserved_at_70[0x3]; u8 log_compress_mmo_size[0x5]; - u8 reserved_at_78[0x3]; + u8 decompress_lz4_data_only_v2[0x1]; + u8 decompress_lz4_no_checksum_v2[0x1]; + u8 decompress_lz4_checksum_v2[0x1]; u8 log_decompress_mmo_size[0x5]; u8 log_max_srq_sz[0x8]; u8 log_max_qp_sz[0x8];