diff mbox series

[v2,03/10] net/txgbe: fix default signal quality value for KX/KX4

Message ID 20230202092132.3271910-4-jiawenwu@trustnetic.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series Wangxun fixes and new supports |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Jiawen Wu Feb. 2, 2023, 9:21 a.m. UTC 
  On old firmware versions, the default value of signal quality(TX_EQ) is
configured by the driver. Fix it for KX/KX4 mode.

Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/base/txgbe_phy.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 9f46d5bdb0..87935abdaa 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1693,9 +1693,10 @@  txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 	} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
 		value = (0x1804 & ~0x3F3F);
+		value |= 40 << 8;
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
-		value = (0x50 & ~0x7F) | 40 | (1 << 6);
+		value = (0x50 & ~0x7F) | (1 << 6);
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 	}
 out:
@@ -1907,10 +1908,10 @@  txgbe_set_link_to_kx(struct txgbe_hw *hw,
 		value |= hw->phy.ffe_post | (1 << 6);
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 	} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
-		value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
+		value = (0x1804 & ~0x3F3F) | (40 << 8);
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
-		value = (0x50 & ~0x7F) | 16 | (1 << 6);
+		value = (0x50 & ~0x7F) | (1 << 6);
 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 	}
 out: