diff mbox series

[v2,04/10] net/mlx5/hws: read cross-vhca capabilities

Message ID 20230105130304.537205-5-erezsh@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series Support resource sharing among ibv_devices |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Erez Shitrit Jan. 5, 2023, 1:02 p.m. UTC 
  From: Yevgeny Kliteynik <kliteyn@nvidia.com>


And keep them for future processing.

Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_cmd.c | 24 ++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_cmd.h |  1 +
 2 files changed, 25 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 721376b8da..2156fd6643 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -723,6 +723,7 @@  int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
 	uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 	const struct flow_hw_port_info *port_info;
 	struct ibv_device_attr_ex attr_ex;
+	u32 res;
 	int ret;
 
 	MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
@@ -798,6 +799,23 @@  int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
 						     capability.cmd_hca_cap_2.
 						     format_select_dw_gtpu_first_ext_dw_0);
 
+	/* check cross-VHCA support in cap2 */
+	res =
+	MLX5_GET(query_hca_cap_out, out,
+		capability.cmd_hca_cap_2.cross_vhca_object_to_object_supported);
+
+	caps->cross_vhca_resources = (res & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
+				     (res & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
+				     (res & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
+
+	res =
+	MLX5_GET(query_hca_cap_out, out,
+		capability.cmd_hca_cap_2.allowed_object_for_other_vhca_access);
+
+	caps->cross_vhca_resources &= (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
+				      (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
+				      (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
+
 	MLX5_SET(query_hca_cap_in, in, op_mod,
 		 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 		 MLX5_HCA_CAP_OPMOD_GET_CUR);
@@ -817,6 +835,12 @@  int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
 					capability.flow_table_nic_cap.
 					flow_table_properties_nic_receive.reparse);
 
+	/* check cross-VHCA support in flow table properties */
+	res =
+	MLX5_GET(query_hca_cap_out, out,
+		capability.flow_table_nic_cap.flow_table_properties_nic_receive.cross_vhca_object);
+	caps->cross_vhca_resources &= res;
+
 	if (caps->wqe_based_update) {
 		MLX5_SET(query_hca_cap_in, in, op_mod,
 			 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 2b3b47f473..ab61e27fd8 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -163,6 +163,7 @@  struct mlx5dr_cmd_query_caps {
 	uint8_t sq_ts_format;
 	uint64_t definer_format_sup;
 	uint32_t trivial_match_definer;
+	bool cross_vhca_resources;
 	char fw_ver[64];
 };