diff mbox series

common/cnxk: reduce channel count per LMAC

Message ID 20230104060712.283128-1-skori@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series common/cnxk: reduce channel count per LMAC |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-abi-testing success Testing PASS

Commit Message

Sunil Kumar Kori Jan. 4, 2023, 6:07 a.m. UTC 
  From: Sunil Kumar Kori <skori@marvell.com>

Due to limitation, imposed by latest kernel, maximum number of
channel supported per LMAC is reduced to 8. Because of this change
application gets failed to initialize for more channels.

Also this limitation impacts PFC functional behaviour.

So patch just aligns the supported number of channel with kernel.

Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
Cc: stable@dpdk.org

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jerin Jacob Jan. 13, 2023, 5:23 a.m. UTC | #1 
On Wed, Jan 4, 2023 at 11:37 AM <skori@marvell.com> wrote:
>
> From: Sunil Kumar Kori <skori@marvell.com>
>
> Due to limitation, imposed by latest kernel, maximum number of
> channel supported per LMAC is reduced to 8. Because of this change
> application gets failed to initialize for more channels.
>
> Also this limitation impacts PFC functional behaviour.
>
> So patch just aligns the supported number of channel with kernel.
>
> Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
> Cc: stable@dpdk.org
>
> Signed-off-by: Sunil Kumar Kori <skori@marvell.com>


Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks

    common/cnxk: reduce channel count per LMAC

    Due to limitation, imposed by latest AF kernel driver, maximum number of
    channel supported per LMAC is reduced to 8. Because of this change
    application gets failed to initialize for more channels.

    Also this limitation impacts PFC functional behaviour.

    So patch just aligns the supported number of channel with AF kernel
    driver.

    Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
    Cc: stable@dpdk.org

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>

> ---
>  drivers/common/cnxk/roc_mbox.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
> index 8b0384c737..fd9d3e73cd 100644
> --- a/drivers/common/cnxk/roc_mbox.h
> +++ b/drivers/common/cnxk/roc_mbox.h
> @@ -1169,7 +1169,7 @@ struct nix_bp_cfg_req {
>   * so maximum 256 channels are possible.
>   */
>  #define NIX_MAX_CHAN    256
> -#define NIX_CGX_MAX_CHAN 16
> +#define NIX_CGX_MAX_CHAN 8
>  #define NIX_LBK_MAX_CHAN 1
>  struct nix_bp_cfg_rsp {
>         struct mbox_msghdr hdr;
> --
> 2.25.1
>
Sunil Kumar Kori Jan. 13, 2023, 6:29 a.m. UTC | #2 
Ack.

Regards
Sunil Kumar Kori

> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Friday, January 13, 2023 10:54 AM
> To: Sunil Kumar Kori <skori@marvell.com>
> Cc: Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>; Kiran Kumar
> Kokkilagadda <kirankumark@marvell.com>; Satha Koteswara Rao Kottidi
> <skoteshwar@marvell.com>; dev@dpdk.org; stable@dpdk.org
> Subject: [EXT] Re: [PATCH] common/cnxk: reduce channel count per LMAC
> 
> External Email
> 
> ----------------------------------------------------------------------
> On Wed, Jan 4, 2023 at 11:37 AM <skori@marvell.com> wrote:
> >
> > From: Sunil Kumar Kori <skori@marvell.com>
> >
> > Due to limitation, imposed by latest kernel, maximum number of channel
> > supported per LMAC is reduced to 8. Because of this change application
> > gets failed to initialize for more channels.
> >
> > Also this limitation impacts PFC functional behaviour.
> >
> > So patch just aligns the supported number of channel with kernel.
> >
> > Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
> 
> 
> Updated the git commit as follows and applied to dpdk-next-net-mrvl/for-
> next-net. Thanks
> 
>     common/cnxk: reduce channel count per LMAC
> 
>     Due to limitation, imposed by latest AF kernel driver, maximum number of
>     channel supported per LMAC is reduced to 8. Because of this change
>     application gets failed to initialize for more channels.
> 
>     Also this limitation impacts PFC functional behaviour.
> 
>     So patch just aligns the supported number of channel with AF kernel
>     driver.
> 
>     Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
>     Cc: stable@dpdk.org
> 
>     Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
> 
> > ---
> >  drivers/common/cnxk/roc_mbox.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/common/cnxk/roc_mbox.h
> > b/drivers/common/cnxk/roc_mbox.h index 8b0384c737..fd9d3e73cd
> 100644
> > --- a/drivers/common/cnxk/roc_mbox.h
> > +++ b/drivers/common/cnxk/roc_mbox.h
> > @@ -1169,7 +1169,7 @@ struct nix_bp_cfg_req {
> >   * so maximum 256 channels are possible.
> >   */
> >  #define NIX_MAX_CHAN    256
> > -#define NIX_CGX_MAX_CHAN 16
> > +#define NIX_CGX_MAX_CHAN 8
> >  #define NIX_LBK_MAX_CHAN 1
> >  struct nix_bp_cfg_rsp {
> >         struct mbox_msghdr hdr;
> > --
> > 2.25.1
> >
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 8b0384c737..fd9d3e73cd 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1169,7 +1169,7 @@  struct nix_bp_cfg_req {
  * so maximum 256 channels are possible.
  */
 #define NIX_MAX_CHAN	 256
-#define NIX_CGX_MAX_CHAN 16
+#define NIX_CGX_MAX_CHAN 8
 #define NIX_LBK_MAX_CHAN 1
 struct nix_bp_cfg_rsp {
 	struct mbox_msghdr hdr;