diff mbox series

net/mlx5/hws: fix incorrect dw_8_6_ext PRM offset

Message ID 20221208110900.8937-1-valex@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5/hws: fix incorrect dw_8_6_ext PRM offset |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS

Commit Message

Alex Vesker Dec. 8, 2022, 11:08 a.m. UTC 
  The offset of format_select_dw_8_6_ext was incorrect.
Update the reserved offsets to correct value.

Fixes: 365cdf5f8ce7 ("net/mlx5/hws: add command layer")
Signed-off-by: Alex Vesker <valex@nvidia.com>
Reviewed-by: Erez Shitrit <erezsh@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Matan Azrad Dec. 12, 2022, 12:48 p.m. UTC | #1 
From: Alex Vesker <valex@nvidia.com>
> Subject: [PATCH] net/mlx5/hws: fix incorrect dw_8_6_ext PRM offset
> 
> The offset of format_select_dw_8_6_ext was incorrect.
> Update the reserved offsets to correct value.
> 
> Fixes: 365cdf5f8ce7 ("net/mlx5/hws: add command layer")
> Signed-off-by: Alex Vesker <valex@nvidia.com>
> Reviewed-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Raslan Darawsheh Dec. 21, 2022, 8:23 a.m. UTC | #2 
Hi,

> -----Original Message-----
> From: Alex Vesker <valex@nvidia.com>
> Sent: Thursday, December 8, 2022 1:09 PM
> To: Alex Vesker <valex@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Suanming Mou <suanmingm@nvidia.com>;
> Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>
> Subject: [PATCH] net/mlx5/hws: fix incorrect dw_8_6_ext PRM offset
> 
> The offset of format_select_dw_8_6_ext was incorrect.
> Update the reserved offsets to correct value.
> 
> Fixes: 365cdf5f8ce7 ("net/mlx5/hws: add command layer")
Missing Cc: stable@dpdk.org

Added during integration

> Signed-off-by: Alex Vesker <valex@nvidia.com>
> Reviewed-by: Erez Shitrit <erezsh@nvidia.com>
> ---

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 2b5c43ee6e..62f39bb413 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2121,10 +2121,11 @@  struct mlx5_ifc_cmd_hca_cap_2_bits {
 	u8 hairpin_sq_wqe_bb_size[0x5];
 	u8 hairpin_sq_wq_in_host_mem[0x1];
 	u8 hairpin_data_buffer_locked[0x1];
-	u8 reserved_at_16a[0x36];
-	u8 reserved_at_1a0[0xb];
+	u8 reserved_at_16a[0x16];
+	u8 reserved_at_180[0x20];
+	u8 reserved_at_1a0[0xa];
 	u8 format_select_dw_8_6_ext[0x1];
-	u8 reserved_at_1ac[0x14];
+	u8 reserved_at_1ac[0x15];
 	u8 general_obj_types_127_64[0x40];
 	u8 reserved_at_200[0x53];
 	u8 flow_counter_bulk_log_max_alloc[0x5];