diff mbox series

net/cnxk: add support for L2 ether ptype for cnxk

Message ID 20221128043327.1472374-1-kirankumark@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series net/cnxk: add support for L2 ether ptype for cnxk |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional fail Functional Testing issues
ci/intel-Testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS

Commit Message

Kiran Kumar Kokkilagadda Nov. 28, 2022, 4:33 a.m. UTC 
  From: Kiran Kumar K <kirankumark@marvell.com>

Adding lookup support for RTE_PTYPE_L2_ETHER in cnxk driver.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 drivers/net/cnxk/cnxk_lookup.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Jerin Jacob Jan. 6, 2023, 9:20 a.m. UTC | #1 
On Mon, Nov 28, 2022 at 10:03 AM <kirankumark@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark@marvell.com>
>
> Adding lookup support for RTE_PTYPE_L2_ETHER in cnxk driver.
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

Updated the git commit subject as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks

    net/cnxk: support L2 ether ptype



> ---
>  drivers/net/cnxk/cnxk_lookup.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c
> index f36fb8f27a..5acf73fe17 100644
> --- a/drivers/net/cnxk/cnxk_lookup.c
> +++ b/drivers/net/cnxk/cnxk_lookup.c
> @@ -15,6 +15,7 @@ cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)
>         RTE_SET_USED(eth_dev);
>
>         static const uint32_t ptypes[] = {
> +               RTE_PTYPE_L2_ETHER,           /* LA */
>                 RTE_PTYPE_L2_ETHER_QINQ,      /* LB */
>                 RTE_PTYPE_L2_ETHER_VLAN,      /* LB */
>                 RTE_PTYPE_L2_ETHER_TIMESYNC,  /* LB */
> @@ -88,19 +89,25 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype)
>                 case NPC_LT_LB_CTAG:
>                         val |= RTE_PTYPE_L2_ETHER_VLAN;
>                         break;
> +               default:
> +                       val |= RTE_PTYPE_L2_ETHER;
>                 }
>
>                 switch (lc) {
>                 case NPC_LT_LC_ARP:
> +                       val = (val & ~RTE_PTYPE_L2_MASK);
>                         val |= RTE_PTYPE_L2_ETHER_ARP;
>                         break;
>                 case NPC_LT_LC_NSH:
> +                       val = (val & ~RTE_PTYPE_L2_MASK);
>                         val |= RTE_PTYPE_L2_ETHER_NSH;
>                         break;
>                 case NPC_LT_LC_FCOE:
> +                       val = (val & ~RTE_PTYPE_L2_MASK);
>                         val |= RTE_PTYPE_L2_ETHER_FCOE;
>                         break;
>                 case NPC_LT_LC_MPLS:
> +                       val = (val & ~RTE_PTYPE_L2_MASK);
>                         val |= RTE_PTYPE_L2_ETHER_MPLS;
>                         break;
>                 case NPC_LT_LC_IP:
> @@ -116,6 +123,7 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype)
>                         val |= RTE_PTYPE_L3_IPV6_EXT;
>                         break;
>                 case NPC_LT_LC_PTP:
> +                       val = (val & ~RTE_PTYPE_L2_MASK);
>                         val |= RTE_PTYPE_L2_ETHER_TIMESYNC;
>                         break;
>                 }
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c
index f36fb8f27a..5acf73fe17 100644
--- a/drivers/net/cnxk/cnxk_lookup.c
+++ b/drivers/net/cnxk/cnxk_lookup.c
@@ -15,6 +15,7 @@  cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 	RTE_SET_USED(eth_dev);
 
 	static const uint32_t ptypes[] = {
+		RTE_PTYPE_L2_ETHER,	      /* LA */
 		RTE_PTYPE_L2_ETHER_QINQ,      /* LB */
 		RTE_PTYPE_L2_ETHER_VLAN,      /* LB */
 		RTE_PTYPE_L2_ETHER_TIMESYNC,  /* LB */
@@ -88,19 +89,25 @@  nix_create_non_tunnel_ptype_array(uint16_t *ptype)
 		case NPC_LT_LB_CTAG:
 			val |= RTE_PTYPE_L2_ETHER_VLAN;
 			break;
+		default:
+			val |= RTE_PTYPE_L2_ETHER;
 		}
 
 		switch (lc) {
 		case NPC_LT_LC_ARP:
+			val = (val & ~RTE_PTYPE_L2_MASK);
 			val |= RTE_PTYPE_L2_ETHER_ARP;
 			break;
 		case NPC_LT_LC_NSH:
+			val = (val & ~RTE_PTYPE_L2_MASK);
 			val |= RTE_PTYPE_L2_ETHER_NSH;
 			break;
 		case NPC_LT_LC_FCOE:
+			val = (val & ~RTE_PTYPE_L2_MASK);
 			val |= RTE_PTYPE_L2_ETHER_FCOE;
 			break;
 		case NPC_LT_LC_MPLS:
+			val = (val & ~RTE_PTYPE_L2_MASK);
 			val |= RTE_PTYPE_L2_ETHER_MPLS;
 			break;
 		case NPC_LT_LC_IP:
@@ -116,6 +123,7 @@  nix_create_non_tunnel_ptype_array(uint16_t *ptype)
 			val |= RTE_PTYPE_L3_IPV6_EXT;
 			break;
 		case NPC_LT_LC_PTP:
+			val = (val & ~RTE_PTYPE_L2_MASK);
 			val |= RTE_PTYPE_L2_ETHER_TIMESYNC;
 			break;
 		}