diff mbox series

net/mlx5: fix available tag registers calculation for HWS

Message ID 20221122125320.2327039-1-dsosnowski@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix available tag registers calculation for HWS |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS

Commit Message

Dariusz Sosnowski Nov. 22, 2022, 12:53 p.m. UTC 
  Before this patch, if two ports in separate switch domains
were probed by an application, the shared array of available TAG
registers was calculated incorrectly.

When the intersection of supported REG_C registers and
available TAG registers was calculated,
capabilities were checked against an index of the TAG array,
not the register stored under that index.

This patch fixes this behavior by comparing capabilities mask
against registers stored in the TAG array.
Available TAG registers calculation is also refactored
to simplify the code.

Fixes: 8a89038f40ca ("net/mlx5: provide available tag registers")
Cc: bingz@nvidia.com

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Reviewed-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 46 +++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 20 deletions(-)

Comments

Raslan Darawsheh Dec. 18, 2022, 12:05 p.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Sent: Tuesday, November 22, 2022 2:53 PM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Bing Zhao <bingz@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Ori Kam
> <orika@nvidia.com>
> Subject: [PATCH] net/mlx5: fix available tag registers calculation for HWS
> 
> Before this patch, if two ports in separate switch domains were probed by an
> application, the shared array of available TAG registers was calculated
> incorrectly.
> 
> When the intersection of supported REG_C registers and available TAG
> registers was calculated, capabilities were checked against an index of the
> TAG array, not the register stored under that index.
> 
> This patch fixes this behavior by comparing capabilities mask against registers
> stored in the TAG array.
> Available TAG registers calculation is also refactored to simplify the code.
> 
> Fixes: 8a89038f40ca ("net/mlx5: provide available tag registers")
> Cc: bingz@nvidia.com
> 
> Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Reviewed-by: Bing Zhao <bingz@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index a3c8056515..20c71ff7f0 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -7178,9 +7178,9 @@  void flow_hw_init_tags_set(struct rte_eth_dev *dev)
 	uint32_t meta_mode = priv->sh->config.dv_xmeta_en;
 	uint8_t masks = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
 	uint32_t i, j;
-	enum modify_reg copy[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON};
+	uint8_t reg_off;
 	uint8_t unset = 0;
-	uint8_t copy_masks = 0;
+	uint8_t common_masks = 0;
 
 	/*
 	 * The CAPA is global for common device but only used in net.
@@ -7195,29 +7195,35 @@  void flow_hw_init_tags_set(struct rte_eth_dev *dev)
 	if (meta_mode == MLX5_XMETA_MODE_META32_HWS)
 		unset |= 1 << (REG_C_1 - REG_C_0);
 	masks &= ~unset;
+	/*
+	 * If available tag registers were previously calculated,
+	 * calculate a bitmask with an intersection of sets of:
+	 * - registers supported by current port,
+	 * - previously calculated available tag registers.
+	 */
 	if (mlx5_flow_hw_avl_tags_init_cnt) {
 		MLX5_ASSERT(mlx5_flow_hw_aso_tag == priv->mtr_color_reg);
 		for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
-			if (mlx5_flow_hw_avl_tags[i] != REG_NON && !!((1 << i) & masks)) {
-				copy[mlx5_flow_hw_avl_tags[i] - REG_C_0] =
-						mlx5_flow_hw_avl_tags[i];
-				copy_masks |= (1 << (mlx5_flow_hw_avl_tags[i] - REG_C_0));
-			}
-		}
-		if (copy_masks != masks) {
-			j = 0;
-			for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++)
-				if (!!((1 << i) & copy_masks))
-					mlx5_flow_hw_avl_tags[j++] = copy[i];
-		}
-	} else {
-		j = 0;
-		for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
-			if (!!((1 << i) & masks))
-				mlx5_flow_hw_avl_tags[j++] =
-					(enum modify_reg)(i + (uint32_t)REG_C_0);
+			if (mlx5_flow_hw_avl_tags[i] == REG_NON)
+				continue;
+			reg_off = mlx5_flow_hw_avl_tags[i] - REG_C_0;
+			if ((1 << reg_off) & masks)
+				common_masks |= (1 << reg_off);
 		}
+		if (common_masks != masks)
+			masks = common_masks;
+		else
+			goto after_avl_tags;
+	}
+	j = 0;
+	for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
+		if ((1 << i) & masks)
+			mlx5_flow_hw_avl_tags[j++] = (enum modify_reg)(i + (uint32_t)REG_C_0);
 	}
+	/* Clear the rest of unusable tag indexes. */
+	for (; j < MLX5_FLOW_HW_TAGS_MAX; j++)
+		mlx5_flow_hw_avl_tags[j] = REG_NON;
+after_avl_tags:
 	priv->sh->hws_tags = 1;
 	mlx5_flow_hw_aso_tag = (enum modify_reg)priv->mtr_color_reg;
 	mlx5_flow_hw_avl_tags_init_cnt++;