From patchwork Thu Nov 17 07:25:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 119926 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90C06A00C2; Thu, 17 Nov 2022 08:26:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1ABB342C4D; Thu, 17 Nov 2022 08:26:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E6E2B42C4D for ; Thu, 17 Nov 2022 08:26:17 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AH6pdSU026293 for ; Wed, 16 Nov 2022 23:26:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=LekQVluYp7u/TPZb2lvzsOdtSoI7Bs9DJFE6rJAcycI=; b=VxCCDR8JUhRPb0i8HYMnNbfGlQSfxwejzByttLsgl3IeOi5UiUHel+cKJDamKUtAKEBQ lW7uLnYjUsAycB+59BRJCrxO/nSok1LYipouErHK2/ep5NhJb3ngJx0iDjQQRSkAYgPE QpUYGiNGgYCFn5XMlbqnqwguoHf+aMc5iK80Y3CxomfuHzUzs6a9d1R2dF6gq+cvpHv3 k0f+rdvdmtVsneb8pf7HHxq2DCCcKyhc+Vu/l/pP3MJM8zxehZIy2eutGYPU7Ekumr0T UnZwah+gw8KXQbYq/maSl8zbzv8IHIVqAXJFVfAIYt5PQVR3h7DIgOCmSoOcaDTBigUs /A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kwg2b030j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 16 Nov 2022 23:26:17 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 16 Nov 2022 23:26:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 16 Nov 2022 23:26:14 -0800 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 65C8A5B6927; Wed, 16 Nov 2022 23:26:11 -0800 (PST) From: Ashwin Sekhar T K To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , , , , Subject: [PATCH v1 3/3] net/cnxk: add debug check for number of Tx descriptors Date: Thu, 17 Nov 2022 12:55:58 +0530 Message-ID: <20221117072558.3582292-3-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117072558.3582292-1-asekhar@marvell.com> References: <20221117072558.3582292-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: diWbYHk0xcoF_zaWHs0UnDn2Hl5gfRJB X-Proofpoint-ORIG-GUID: diWbYHk0xcoF_zaWHs0UnDn2Hl5gfRJB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-17_04,2022-11-16_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When SG2 descriptors are used and more than 5 segments are present, in certain combination of segments the number of descriptors required will be greater than 16. In debug builds, add an assert to capture this scenario. Signed-off-by: Ashwin Sekhar T K --- drivers/net/cnxk/cn10k_tx.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 3f08a8a473..09c332b2b5 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -84,6 +84,22 @@ cn10k_nix_mbuf_sg_dwords(struct rte_mbuf *m) return (segw + 1) / 2; } +static __plt_always_inline void +cn10k_nix_tx_mbuf_validate(struct rte_mbuf *m, const uint32_t flags) +{ +#ifdef RTE_LIBRTE_MBUF_DEBUG + uint16_t segdw; + + segdw = cn10k_nix_mbuf_sg_dwords(m); + segdw += 1 + !!(flags & NIX_TX_NEED_EXT_HDR) + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F); + + PLT_ASSERT(segdw <= 8); +#else + RTE_SET_USED(m); + RTE_SET_USED(flags); +#endif +} + static __plt_always_inline void cn10k_nix_vwqe_wait_fc(struct cn10k_eth_txq *txq, int64_t req) { @@ -1307,6 +1323,8 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws, } for (i = 0; i < burst; i++) { + cn10k_nix_tx_mbuf_validate(tx_pkts[i], flags); + /* Perform header writes for TSO, barrier at * lmt steorl will suffice. */ @@ -1906,6 +1924,8 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, for (j = 0; j < NIX_DESCS_PER_LOOP; j++) { struct rte_mbuf *m = tx_pkts[j]; + cn10k_nix_tx_mbuf_validate(m, flags); + /* Get dwords based on nb_segs. */ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F && flags & NIX_TX_MULTI_SEG_F))