From patchwork Mon Nov 14 10:53:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 119820 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60725A0032; Mon, 14 Nov 2022 11:53:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5095042D0C; Mon, 14 Nov 2022 11:53:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 928C742C29 for ; Mon, 14 Nov 2022 11:53:50 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AE6h1Yd008489 for ; Mon, 14 Nov 2022 02:53:50 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=WDf8uCiMBsnWClgmjR7/ccBPwj5DlbHMYRgBu3AQ0Bw=; b=a+3AIOEojYah+sQaf8/Nez80gVpE8kIkhDJzieK5Hjq8I0+NvpyXd/eTQjNq3Sq+CXlt pKISk0XzLzbkEYmmDCSDuhlvveVMNgE77AolgRO5VdUDGYZcaRTB7viL0CXbwmu8/kr6 cVWNGQiY6Izb0XTE7cU0ZPGxpMNG32AtTmtxyurX1ujq5mVqo2+dG31UTPeIcbjxKC1M B/M223Pkwy1Okgo96jBznn9xThVu9wew8g/2mgn3qletvxxAd4abm3zTC5ZexTL1ZNzs UluRjPP3Yi05QnVdasceyFGMMFWoXMEyn5TT+VMhm0mJY4Z/J8nVI+32obW3tNh04qfn QQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kugnb0rf0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 14 Nov 2022 02:53:49 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 14 Nov 2022 02:53:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Nov 2022 02:53:47 -0800 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id EABDB5C68E9; Mon, 14 Nov 2022 02:53:44 -0800 (PST) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH 2/2] net/cnxk: update IPsec completion code handling Date: Mon, 14 Nov 2022 16:23:21 +0530 Message-ID: <20221114105321.163430-2-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114105321.163430-1-rbhansali@marvell.com> References: <20221114105321.163430-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wlkcssh_z1hhEHI2gRtdofmvsRGJCOha X-Proofpoint-GUID: wlkcssh_z1hhEHI2gRtdofmvsRGJCOha X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-14_10,2022-11-11_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update IPsec handling with reference from UCODE version OCPT-04-IE-IPSEC-MC-30-01-28-00 Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_rx.h | 170 ++++++++++++++++++++---------------- 1 file changed, 95 insertions(+), 75 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 4e22ceda02..ff01c2d8b3 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -42,17 +42,12 @@ (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) : \ (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o))) -#define NIX_RX_SEC_UCC_CONST \ - ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 | \ - ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ - << 24 | \ - ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \ - << 32 | \ - ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ - << 40 | \ - ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ - << 48 | \ - (RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56) +#define NIX_RX_SEC_UCC_CONST \ + ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 8 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) << 16 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 32 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) << 48) #ifdef RTE_LIBRTE_MEMPOOL_DEBUG static inline void @@ -475,16 +470,23 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base, inner->data_len = len; *(uint64_t *)(&inner->rearm_data) = mbuf_init; - inner->ol_flags = ((ucc == CPT_COMP_WARN) ? + inner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ? RTE_MBUF_F_RX_SEC_OFFLOAD : (RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); ucc = hdr->w3.uc_ccode; - inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? - ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) - & 0xFF) << 1 : 0; - } else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) { + + if (ucc && ucc < 0xED) { + inner->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + } else { + ucc += 3; /* To make codes in 0xFx series except 0 */ + inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? + ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) + & 0xFF) << 1 : RTE_MBUF_F_RX_IP_CKSUM_GOOD; + } + } else if ((!(hdr->w0.err_sum) || roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) && + !(hdr->w0.reas_sts)) { /* Reassembly success */ inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, mbuf_init); @@ -541,15 +543,21 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base, inner->data_len = len; *(uint64_t *)(&inner->rearm_data) = mbuf_init; - inner->ol_flags = ((ucc == CPT_COMP_WARN) ? + inner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ? RTE_MBUF_F_RX_SEC_OFFLOAD : (RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); ucc = hdr->w3.uc_ccode; - inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? - ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) - & 0xFF) << 1 : 0; + + if (ucc && ucc < 0xED) { + inner->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + } else { + ucc += 3; /* To make codes in 0xFx series except 0 */ + inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? + ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) + & 0xFF) << 1 : RTE_MBUF_F_RX_IP_CKSUM_GOOD; + } /* Store meta in lmtline to free * Assume all meta's from same aura. @@ -596,7 +604,8 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa, RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1); if (flags & NIX_RX_REAS_F && hdr->w0.num_frags) { - if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) { + if ((!(hdr->w0.err_sum) || roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) && + !(hdr->w0.reas_sts)) { /* Reassembly success */ nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, mbuf_init); @@ -1317,6 +1326,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, uintptr_t cpth1 = (uintptr_t)mbuf1 + d_off; uintptr_t cpth2 = (uintptr_t)mbuf2 + d_off; uintptr_t cpth3 = (uintptr_t)mbuf3 + d_off; + uint8_t code; uint64x2_t inner0, inner1, inner2, inner3; uint64x2_t wqe01, wqe23, sa01, sa23; @@ -1352,42 +1362,46 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, sa01 = vaddq_u64(sa01, vdupq_n_u64(sa_base)); sa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base)); - const uint8x16_t tbl = { - /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */ - 0, - /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */ - RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1, - /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */ - 0, - /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */ - (RTE_MBUF_F_RX_IP_CKSUM_GOOD | - RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, - /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */ - (RTE_MBUF_F_RX_IP_CKSUM_GOOD | - RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1, - /* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */ - (RTE_MBUF_F_RX_IP_CKSUM_GOOD | - RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, - /* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */ - (RTE_MBUF_F_RX_IP_CKSUM_GOOD | - RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, - /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */ - RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1, - /* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */ - 1, 0, 1, 1, 1, 1, 0, 1, - }; - - const int8x8_t err_off = { - /* UCC of significance starts from 0xF0 */ - 0xF0, - /* Move HW_CCODE from 0:6 -> 8:14 */ - -8, - 0xF0, - -8, - 0xF0, - -8, - 0xF0, - -8, + const uint8x16x2_t tbl = {{ + { + /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */ + RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1, + 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + 3, 1, 3, 3, 3, 3, 1, 3, 1, + }, + { + 1, 1, 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */ + RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1, + /* Rest 0 to indicate RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }}; + + const uint8x8_t err_off = { + /* UCC */ + 0xED, + /* HW_CCODE 0:6 -> 7:D */ + -7, + 0xED, + -7, + 0xED, + -7, + 0xED, + -7, }; ucc = vdup_n_u8(0); @@ -1395,8 +1409,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, ucc = vset_lane_u16(*(uint16_t *)(cpth1 + 30), ucc, 1); ucc = vset_lane_u16(*(uint16_t *)(cpth2 + 30), ucc, 2); ucc = vset_lane_u16(*(uint16_t *)(cpth3 + 30), ucc, 3); - ucc = vsub_s8(ucc, err_off); - ucc = vqtbl1_u8(tbl, ucc); + ucc = vsub_u8(ucc, err_off); + + /* Table lookup to get the corresponding flags, Out of the range + * from this lookup will have value 0 and consider as + * RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED. + */ + ucc = vqtbl2_u8(tbl, ucc); RTE_BUILD_BUG_ON(NPC_LT_LC_IP != 2); RTE_BUILD_BUG_ON(NPC_LT_LC_IP_OPT != 3); @@ -1478,10 +1497,11 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa, cpth0, mbuf0, &f0, &ol_flags0, flags, &rearm0); - ol_flags0 |= ((uint64_t)vget_lane_u8(ucc, 0)) - << 1; - ol_flags0 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | - (uint64_t)vget_lane_u8(ucc, 1) << 19); + code = vget_lane_u8(ucc, 0); + ol_flags0 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) : + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + + ol_flags0 |= ((uint64_t)(vget_lane_u8(ucc, 1)) << 18); } if (cq1_w1 & BIT(11)) { @@ -1502,10 +1522,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa, cpth1, mbuf1, &f1, &ol_flags1, flags, &rearm1); - ol_flags1 |= ((uint64_t)vget_lane_u8(ucc, 2)) - << 1; - ol_flags1 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | - (uint64_t)vget_lane_u8(ucc, 3) << 19); + code = vget_lane_u8(ucc, 2); + ol_flags1 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) : + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + ol_flags1 |= ((uint64_t)(vget_lane_u8(ucc, 3)) << 18); } if (cq2_w1 & BIT(11)) { @@ -1526,10 +1546,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa, cpth2, mbuf2, &f2, &ol_flags2, flags, &rearm2); - ol_flags2 |= ((uint64_t)vget_lane_u8(ucc, 4)) - << 1; - ol_flags2 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | - (uint64_t)vget_lane_u8(ucc, 5) << 19); + code = vget_lane_u8(ucc, 4); + ol_flags2 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) : + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + ol_flags2 |= ((uint64_t)(vget_lane_u8(ucc, 5)) << 18); } if (cq3_w1 & BIT(11)) { @@ -1550,10 +1570,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa, cpth3, mbuf3, &f3, &ol_flags3, flags, &rearm3); - ol_flags3 |= ((uint64_t)vget_lane_u8(ucc, 6)) - << 1; - ol_flags3 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | - (uint64_t)vget_lane_u8(ucc, 7) << 19); + code = vget_lane_u8(ucc, 6); + ol_flags3 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) : + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + ol_flags3 |= ((uint64_t)(vget_lane_u8(ucc, 7)) << 18); } }