diff mbox series

[v3,1/3] eal: add 8 bits case for wait scheme

Message ID 20221111072649.3304429-2-feifei.wang2@arm.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series Enable PMD power management on Arm |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Feifei Wang Nov. 11, 2022, 7:26 a.m. UTC 
  For wait scheme generic helper, add 8 bits case.

Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 lib/eal/arm/include/rte_pause_64.h | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h
index fe4d42b1ea..c21600ca96 100644
--- a/lib/eal/arm/include/rte_pause_64.h
+++ b/lib/eal/arm/include/rte_pause_64.h
@@ -31,6 +31,25 @@  static inline void rte_pause(void)
 /* Put processor into low power WFE(Wait For Event) state. */
 #define __RTE_ARM_WFE() { asm volatile("wfe" : : : "memory"); }
 
+/*
+ * Atomic exclusive load from addr, it returns the 8-bit content of
+ * *addr while making it 'monitored', when it is written by someone
+ * else, the 'monitored' state is cleared and an event is generated
+ * implicitly to exit WFE.
+ */
+#define __RTE_ARM_LOAD_EXC_8(src, dst, memorder) {       \
+	if (memorder == __ATOMIC_RELAXED) {               \
+		asm volatile("ldxrb %w[tmp], [%x[addr]]"  \
+			: [tmp] "=&r" (dst)               \
+			: [addr] "r" (src)                \
+			: "memory");                      \
+	} else {                                          \
+		asm volatile("ldaxrb %w[tmp], [%x[addr]]" \
+			: [tmp] "=&r" (dst)               \
+			: [addr] "r" (src)                \
+			: "memory");                      \
+	} }
+
 /*
  * Atomic exclusive load from addr, it returns the 16-bit content of
  * *addr while making it 'monitored', when it is written by someone
@@ -111,9 +130,11 @@  static inline void rte_pause(void)
 	} }                                                             \
 
 #define __RTE_ARM_LOAD_EXC(src, dst, memorder, size) {     \
-	RTE_BUILD_BUG_ON(size != 16 && size != 32 &&       \
-		size != 64 && size != 128);                \
-	if (size == 16)                                    \
+	RTE_BUILD_BUG_ON(size != 8 && size != 16 &&        \
+		size != 32 && size != 64 && size != 128);  \
+	if (size == 8)                                    \
+		__RTE_ARM_LOAD_EXC_8(src, dst, memorder)   \
+	else if (size == 16)                               \
 		__RTE_ARM_LOAD_EXC_16(src, dst, memorder)  \
 	else if (size == 32)                               \
 		__RTE_ARM_LOAD_EXC_32(src, dst, memorder)  \