Message ID | 20221031160824.330200-3-michaelba@nvidia.com (mailing list archive) |
---|---|
State | Accepted, archived |
Delegated to: | Raslan Darawsheh |
Headers |
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Mon, 31 Oct 2022 09:08:31 -0700 From: Michael Baum <michaelba@nvidia.com> To: <dev@dpdk.org> CC: Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <jackmin@nvidia.com> Subject: [PATCH 2/5] net/mlx5: fix accessing the wrong counter Date: Mon, 31 Oct 2022 18:08:21 +0200 Message-ID: <20221031160824.330200-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031160824.330200-1-michaelba@nvidia.com> References: <20221031160824.330200-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT010:EE_|CH2PR12MB4328:EE_ X-MS-Office365-Filtering-Correlation-Id: 01f14294-2aea-46ed-1904-08dabb5a2e5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t9Bu7QX6VbP2+ouREAu40IJh4oWntLyq5zwVEm+SqyT5ILy55B0lpxdVekg9zKmIxJzLVuEP2RJf5qulqP5Go2LngpQsnUrPt/unR36Gcv8wryUEUeifgeAQV7N38AFTv/FL5D1zqZsd8T1bEo/Dnz+vlVhS5ZLLOmNsNQmvKAL9Ax0F+pzS5iYJJooHLdeOyzeFVTPfUjDNGStyVNZrwTPA0sLOsLsjR9HFZH76CDHhI9xgwIZ3QzIaofPBFcxK+qPr6sLFPmCtbG63U8rK9IqrgCWcLqfrQL3irbziN5FDDW/f5QgMVLDMwQNO37gV4AOzWjvootgeQmR4xTu6VifBOp/abky0/YBDieFdJQST+R5p12obP+c/Yk0vkznqZNGhldKFos2MWyG7tGktu9rBjSFRuF5YMswpSc+OIErHczRUR8jPulioN53bT+nqNO0YdMpeEEupcPa1acpoPWAf3kovyOMlteCkCaa1fs4Bos9KnZIWizDjn+1krsl/cdxuqcVmZHjSRwah23M/AQNAN1OYPlXP7JsgWld6IKXYpu0ww6ZA/O2I5NwA1eP8ksvkDWtRJOsQxGk/k+nOd67p7tV7NFOul7apagRCrZ/Z+KONhfC+nY29LsrWEwBwK2/ZavArXgDZyQ9Gp6E80k7Ajg+66ykQ716mFvfVt24kIu22/y6//tZJP9/iYnVGUM3EF4CMuMtwF/QEVWQkGk6Thx7P8hwTAaD4c0VnCJlHBxj56Vdy9BdGsff35VfaazNnP9ytYKD8ZEycNHxqrw== X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Series |
net/mlx5: some counter fixes
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Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | success | coding style OK |
Commit Message
Michael Baum
Oct. 31, 2022, 4:08 p.m. UTC
The HWS counter has 2 different identifiers: 1. Type "cnt_id_t" which represents the counter inside caches and in the flow structure. This index cannot be zero and is mostly called "cnt_id". 2. Internal index, the index in counters array with type "uint32_t". mostly it is called "iidx". The second ID is calculated from the first using "mlx5_hws_cnt_iidx()" function. When a direct counter is allocated, if the queue cache is not empty, the counter represented by cnt_id is popped from the cache. This counter may be invalid according to the query_gen field. Thus, the "iidx" is parsed from cnt_id and if it is valid, it is used to update the fields of the counter structure. When this counter is invalid, all the cache is flashed and new counters are fetched into the cache. After fetching, another counter represented by cnt_id is taken from the cache. Unfortunately, for updating fields like "in_used" or "age_idx", the function wrongly may use the old "iidx" coming from an invalid cnt_id. Update the "iidx" in case of an invalid counter popped from the cache. Fixes: 4d368e1da3a4 ("net/mlx5: support flow counter action for HWS") Cc: jackmin@nvidia.com Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> Acked-by: Xiaoyu Min <jackmin@nvidia.com> --- drivers/net/mlx5/mlx5_hws_cnt.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h index e311923f71..196604aded 100644 --- a/drivers/net/mlx5/mlx5_hws_cnt.h +++ b/drivers/net/mlx5/mlx5_hws_cnt.h @@ -506,6 +506,7 @@ mlx5_hws_cnt_pool_get(struct mlx5_hws_cnt_pool *cpool, uint32_t *queue, rte_ring_dequeue_zc_burst_elem_start(qcache, sizeof(cnt_id_t), 1, &zcdc, NULL); *cnt_id = *(cnt_id_t *)zcdc.ptr1; + iidx = mlx5_hws_cnt_iidx(cpool, *cnt_id); } __hws_cnt_query_raw(cpool, *cnt_id, &cpool->pool[iidx].reset.hits, &cpool->pool[iidx].reset.bytes);