diff mbox series

net/mlx5: enable flow aging action

Message ID 20221031082044.8106-1-suanmingm@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: enable flow aging action |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/github-robot: build fail github build: failed
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Suanming Mou Oct. 31, 2022, 8:20 a.m. UTC 
  As the queue-based aging API has been integrated[1], the flow aging
action support in HWS steering code can be enabled now.

[1]: https://patchwork.dpdk.org/project/dpdk/cover/20221026214943.3686635-1-michaelba@nvidia.com/

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c    |  2 --
 drivers/net/mlx5/mlx5_flow_hw.c |  2 --
 drivers/net/mlx5/mlx5_hws_cnt.c | 11 -----------
 3 files changed, 15 deletions(-)

Comments

Matan Azrad Oct. 31, 2022, 1:57 p.m. UTC | #1 
> As the queue-based aging API has been integrated[1], the flow aging action
> support in HWS steering code can be enabled now.
> 
> [1]:
> https://patchwork.dpdk.org/project/dpdk/cover/20221026214943.3686635-
> 1-michaelba@nvidia.com/
> 
> Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Raslan Darawsheh Nov. 3, 2022, 11:40 a.m. UTC | #2 
Hi,

> -----Original Message-----
> From: Suanming Mou <suanmingm@nvidia.com>
> Sent: Monday, October 31, 2022 10:21 AM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>
> Subject: [PATCH] net/mlx5: enable flow aging action
> 
> As the queue-based aging API has been integrated[1], the flow aging action
> support in HWS steering code can be enabled now.
> 
> [1]:
> https://patchwork.dpdk.org/project/dpdk/cover/20221026214943.3686635-
> 1-michaelba@nvidia.com/
> 
> Signed-off-by: Suanming Mou <suanmingm@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 8e7d649d15..e28587da8e 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1084,9 +1084,7 @@  static const struct rte_flow_ops mlx5_flow_ops = {
 	.isolate = mlx5_flow_isolate,
 	.query = mlx5_flow_query,
 	.dev_dump = mlx5_flow_dev_dump,
-#ifdef MLX5_HAVE_RTE_FLOW_Q_AGE
 	.get_q_aged_flows = mlx5_flow_get_q_aged_flows,
-#endif
 	.get_aged_flows = mlx5_flow_get_aged_flows,
 	.action_handle_create = mlx5_action_handle_create,
 	.action_handle_destroy = mlx5_action_handle_destroy,
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 2d275ad111..0e904e4dea 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -7032,10 +7032,8 @@  flow_hw_configure(struct rte_eth_dev *dev,
 		goto err;
 	if (_queue_attr)
 		mlx5_free(_queue_attr);
-#ifdef MLX5_HAVE_RTE_FLOW_Q_AGE
 	if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
 		priv->hws_strict_queue = 1;
-#endif
 	return 0;
 err:
 	if (priv->hws_ctpool) {
diff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c
index b8ce69af57..534a4d76ce 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.c
+++ b/drivers/net/mlx5/mlx5_hws_cnt.c
@@ -846,7 +846,6 @@  int
 mlx5_hws_age_action_update(struct mlx5_priv *priv, uint32_t idx,
 			   const void *update, struct rte_flow_error *error)
 {
-#ifdef MLX5_HAVE_RTE_FLOW_Q_AGE
 	const struct rte_flow_update_age *update_ade = update;
 	struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
 	struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
@@ -899,14 +898,6 @@  mlx5_hws_age_action_update(struct mlx5_priv *priv, uint32_t idx,
 					 __ATOMIC_RELAXED);
 	}
 	return 0;
-#else
-	RTE_SET_USED(priv);
-	RTE_SET_USED(idx);
-	RTE_SET_USED(update);
-	return rte_flow_error_set(error, ENOTSUP,
-				  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
-				  "update age action not supported");
-#endif
 }
 
 /**
@@ -1193,9 +1184,7 @@  mlx5_hws_age_pool_init(struct rte_eth_dev *dev,
 	uint32_t nb_ages_updated;
 	int ret;
 
-#ifdef MLX5_HAVE_RTE_FLOW_Q_AGE
 	strict_queue = !!(attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
-#endif
 	MLX5_ASSERT(priv->hws_cpool);
 	nb_alloc_cnts = mlx5_hws_cnt_pool_get_size(priv->hws_cpool);
 	if (strict_queue) {