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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT063.mail.protection.outlook.com (10.13.172.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Wed, 26 Oct 2022 02:09:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Tue, 25 Oct 2022 19:09:31 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 25 Oct 2022 19:09:29 -0700 From: Suanming Mou To: Matan Azrad , Viacheslav Ovsiienko CC: , Subject: [PATCH] net/mlx5: fix assert failure in item translation Date: Wed, 26 Oct 2022 05:09:13 +0300 Message-ID: <20221026020913.4468-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT063:EE_|DM4PR12MB6469:EE_ X-MS-Office365-Filtering-Correlation-Id: d037b293-4a70-40a8-24dc-08dab6f71ecd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2022 02:09:31.4565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d037b293-4a70-40a8-24dc-08dab6f71ecd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6469 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When HW Steering is enabled, mlx5dr translates flow items using DV item translation functions to configure flows in root flow table. Represented port item stores vport metadata tag in thread-local workspace when translate to DV spec. Due to the thread-local workspace was not created in HW Steering, it caused an assertion in mlx5_flow_get_thread_workspace() This patch adds initialization of thread-local workspace when flow items are translated to DV spec in HW Steering mode. Fixes: cfddba76af4f ("net/mlx5: add hardware steering item translation function") Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 8 ++------ drivers/net/mlx5/mlx5_flow.h | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 20 +++++++++++++------- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 13f7b92d6b..8e7d649d15 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -81,10 +81,6 @@ tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, uint32_t group, uint32_t *table, struct rte_flow_error *error); -static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); -static void mlx5_flow_pop_thread_workspace(void); - - /** Device flow drivers. */ extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; @@ -7586,7 +7582,7 @@ flow_alloc_thread_workspace(void) * * @return pointer to thread specific flow workspace data, NULL on error. */ -static struct mlx5_flow_workspace* +struct mlx5_flow_workspace* mlx5_flow_push_thread_workspace(void) { struct mlx5_flow_workspace *curr; @@ -7623,7 +7619,7 @@ mlx5_flow_push_thread_workspace(void) * * @return pointer to thread specific flow workspace data, NULL on error. */ -static void +void mlx5_flow_pop_thread_workspace(void) { struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 85d2fd219d..da9b65d8fe 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1920,6 +1920,8 @@ struct mlx5_flow_driver_ops { /* mlx5_flow.c */ +struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); +void mlx5_flow_pop_thread_workspace(void); struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); __extension__ struct flow_grp_info { diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f65407bd52..1e52278191 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -13499,6 +13499,7 @@ flow_dv_translate_items_hws(const struct rte_flow_item *items, uint8_t *match_criteria, struct rte_flow_error *error) { + struct mlx5_flow_workspace *flow_wks = mlx5_flow_push_thread_workspace(); struct mlx5_flow_rss_desc rss_desc = { .level = attr->rss_level }; struct rte_flow_attr rattr = { .group = attr->group, @@ -13515,17 +13516,20 @@ flow_dv_translate_items_hws(const struct rte_flow_item *items, .attr = &rattr, .rss_desc = &rss_desc, }; - int ret; + int ret = 0; + RTE_SET_USED(flow_wks); for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { - if (!mlx5_flow_os_item_supported(items->type)) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ITEM, - NULL, "item not supported"); + if (!mlx5_flow_os_item_supported(items->type)) { + ret = rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "item not supported"); + goto exit; + } ret = flow_dv_translate_items(&rte_eth_devices[attr->port_id], items, &wks, key, key_type, NULL); if (ret) - return ret; + goto exit; } if (wks.item_flags & MLX5_FLOW_ITEM_INTEGRITY) { flow_dv_translate_item_integrity_post(key, @@ -13569,7 +13573,9 @@ flow_dv_translate_items_hws(const struct rte_flow_item *items, *match_criteria = flow_dv_matcher_enable(key); if (item_flags) *item_flags = wks.item_flags; - return 0; +exit: + mlx5_flow_pop_thread_workspace(); + return ret; } /**