From patchwork Tue Oct 25 16:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 119115 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E538DA054A; Tue, 25 Oct 2022 18:11:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8DC3542BDC; Tue, 25 Oct 2022 18:11:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A93CD427F6 for ; Tue, 25 Oct 2022 18:11:31 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29PFUif3008950 for ; Tue, 25 Oct 2022 09:11:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=wuWRzm9LYaxC3O1hifEYoVnavMzAUMelvrl96ptnhAY=; b=haxM0e2VNnP9z5EVctDGD6PqQg4zOpy7AxXcHOJ2W4U9aV9bNCMQCXBpT0tTm5J4bY6v ITyGwUHcYL8WUSKjnk/5HoeMhiRnZvb5WyGliPeWfgvdqF0VFaq+2CWD6iwsfZ5XuZVH 8KBymHsfH+ZDUNFro7BrcP6dqSCKYxaq0H/VsI5kndNEBad3sRfErlrXAEugk+KBlE88 /5w/1u9rYcl38xz6C66mumqd8Ndxl4N3PfRKblEJCt6PxgsMn54eMuB5AfbcmgrrJWQP +EWVea97d0l3JPfh+0+szxQhAyX9YI8JP+SDryaU4mOj9LRC7GONb2gGalNPjpBJLwNM DQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kcg1mux7w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 25 Oct 2022 09:11:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Oct 2022 09:11:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Oct 2022 09:11:28 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id DCF573F7087; Tue, 25 Oct 2022 09:11:25 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH v2] event/cnxk: fix incorrect mbuf offset calculation Date: Tue, 25 Oct 2022 21:41:29 +0530 Message-ID: <20221025161129.15933-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025154653.10482-1-pbhagavatula@marvell.com> References: <20221025154653.10482-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7iLSuFtGkSHKo-0CNYILfQlZBnlkYmQC X-Proofpoint-GUID: 7iLSuFtGkSHKo-0CNYILfQlZBnlkYmQC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-25_09,2022-10-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Fix incorrect mbuf offset calculation when HEADROOM exceeds 128B while processing event vectors. Fixes: 7fbbc981d54f("event/cnxk: support vectorized Rx event fast path") Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Remove internal Change-Id. drivers/net/cnxk/cn10k_rx.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 46488d442e..f562a75245 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -1201,9 +1201,11 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, mbuf23 = vqsubq_u64(mbuf23, data_off); } else { mbuf01 = - vsubq_u64(vld1q_u64((uint64_t *)cq0), data_off); - mbuf23 = vsubq_u64(vld1q_u64((uint64_t *)(cq0 + 16)), - data_off); + vsubq_u64(vld1q_u64((uint64_t *)cq0), + vdupq_n_u64(sizeof(struct rte_mbuf))); + mbuf23 = + vsubq_u64(vld1q_u64((uint64_t *)(cq0 + 16)), + vdupq_n_u64(sizeof(struct rte_mbuf))); } /* Move mbufs to scalar registers for future use */