diff mbox series

[v5,02/18] net/mlx5: fix IPv6 and TCP RSS hash fields

Message ID 20221020032210.30250-3-suanmingm@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: HW steering PMD update |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Suanming Mou Oct. 20, 2022, 3:21 a.m. UTC 
  In the flow_dv_hashfields_set() function, while item_flags was 0,
the code went directly to the first if and the else case would
never have chance be checked. This caused the IPv6 and TCP hash
fields in the else case would never be set.

This commit adds the dedicate HW steering hash field set function
to generate the RSS hash fields.

Fixes: 3a2f674b6aa8 ("net/mlx5: add queue and RSS HW steering action")
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 12 +++----
 drivers/net/mlx5/mlx5_flow_hw.c | 59 ++++++++++++++++++++++++++++++++-
 2 files changed, 62 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 0cf757898d..29d7bf7049 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -11274,8 +11274,7 @@  flow_dv_hashfields_set(uint64_t item_flags,
 		rss_inner = 1;
 #endif
 	if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
-	    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||
-	     !items) {
+	    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
 		if (rss_types & MLX5_IPV4_LAYER_TYPES) {
 			if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
 				fields |= IBV_RX_HASH_SRC_IPV4;
@@ -11285,8 +11284,7 @@  flow_dv_hashfields_set(uint64_t item_flags,
 				fields |= MLX5_IPV4_IBV_RX_HASH;
 		}
 	} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
-		   (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||
-		   !items) {
+		   (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
 		if (rss_types & MLX5_IPV6_LAYER_TYPES) {
 			if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
 				fields |= IBV_RX_HASH_SRC_IPV6;
@@ -11309,8 +11307,7 @@  flow_dv_hashfields_set(uint64_t item_flags,
 		return;
 	}
 	if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
-	    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||
-	    !items) {
+	    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
 		if (rss_types & RTE_ETH_RSS_UDP) {
 			if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
 				fields |= IBV_RX_HASH_SRC_PORT_UDP;
@@ -11320,8 +11317,7 @@  flow_dv_hashfields_set(uint64_t item_flags,
 				fields |= MLX5_UDP_IBV_RX_HASH;
 		}
 	} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
-		   (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||
-		   !items) {
+		   (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
 		if (rss_types & RTE_ETH_RSS_TCP) {
 			if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
 				fields |= IBV_RX_HASH_SRC_PORT_TCP;
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index fecf28c1ca..d46e4c6769 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -62,6 +62,63 @@  flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)
 	priv->mark_enabled = enable;
 }
 
+/**
+ * Set the hash fields according to the @p rss_desc information.
+ *
+ * @param[in] rss_desc
+ *   Pointer to the mlx5_flow_rss_desc.
+ * @param[out] hash_fields
+ *   Pointer to the RSS hash fields.
+ */
+static void
+flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
+		       uint64_t *hash_fields)
+{
+	uint64_t fields = 0;
+	int rss_inner = 0;
+	uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
+
+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
+	if (rss_desc->level >= 2)
+		rss_inner = 1;
+#endif
+	if (rss_types & MLX5_IPV4_LAYER_TYPES) {
+		if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
+			fields |= IBV_RX_HASH_SRC_IPV4;
+		else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
+			fields |= IBV_RX_HASH_DST_IPV4;
+		else
+			fields |= MLX5_IPV4_IBV_RX_HASH;
+	} else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
+		if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
+			fields |= IBV_RX_HASH_SRC_IPV6;
+		else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
+			fields |= IBV_RX_HASH_DST_IPV6;
+		else
+			fields |= MLX5_IPV6_IBV_RX_HASH;
+	}
+	if (rss_types & RTE_ETH_RSS_UDP) {
+		if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
+			fields |= IBV_RX_HASH_SRC_PORT_UDP;
+		else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
+			fields |= IBV_RX_HASH_DST_PORT_UDP;
+		else
+			fields |= MLX5_UDP_IBV_RX_HASH;
+	} else if (rss_types & RTE_ETH_RSS_TCP) {
+		if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
+			fields |= IBV_RX_HASH_SRC_PORT_TCP;
+		else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
+			fields |= IBV_RX_HASH_DST_PORT_TCP;
+		else
+			fields |= MLX5_TCP_IBV_RX_HASH;
+	}
+	if (rss_types & RTE_ETH_RSS_ESP)
+		fields |= IBV_RX_HASH_IPSEC_SPI;
+	if (rss_inner)
+		fields |= IBV_RX_HASH_INNER;
+	*hash_fields = fields;
+}
+
 /**
  * Generate the pattern item flags.
  * Will be used for shared RSS action.
@@ -225,7 +282,7 @@  flow_hw_tir_action_register(struct rte_eth_dev *dev,
 		       MLX5_RSS_HASH_KEY_LEN);
 		rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
 		rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
-		flow_dv_hashfields_set(0, &rss_desc, &rss_desc.hash_fields);
+		flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
 		flow_dv_action_rss_l34_hash_adjust(rss->types,
 						   &rss_desc.hash_fields);
 		if (rss->level > 1) {