From patchwork Wed Oct 19 00:38:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118439 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E69BBA0560; Tue, 18 Oct 2022 18:43:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04A93427F2; Tue, 18 Oct 2022 18:42:54 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 8825A40395; Tue, 18 Oct 2022 18:42:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111369; x=1697647369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E0M4heqfM0odSwlFVEGhnhGPzHHBEmhQndghAmwhWNg=; b=G2s/kY2L1adRaFHvYA0AO1nUsNCPUId07lSrcaQkhBSgApYAjof0CgA0 D95cG+UkUwLOqxiSgIeqeSFCUHMJCzXCt5c1KP/bJkgc6YvAiz8FEcmjC UF0qQmCheWi6CfI+spzRFfgAGKXyXPZahROg3QW805Q0MZwTiVQLIwG+R AUFoCI4Im7KQ6NwJZrZTrPdnqMz6ndRBnswx3gZCAk9s3+von4utRY+F6 HgyX2yRMD0Z7ANoQnkx9lBvR6PtjfBDS9lXDAzO9AJKQ2ptg4wnr4FDa5 GfG3mCzR4h32nKbWcRpMVNPUmvj1zSXK5TTEh0mu6v/s2YyDABCXrfKkX A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192040" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192040" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836008" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836008" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:48 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 04/30] baseband/acc100: add LDPC encoder padding function Date: Tue, 18 Oct 2022 17:38:52 -0700 Message-Id: <20221019003918.257506-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LDPC Encoder input may need to be padded to avoid small beat for ACC100. Padding 5GDL input buffer length (BLEN) to avoid case (BLEN % 64) <= 8. Adding protection for corner case to avoid for 5GDL occurrence of last beat within the ACC100 fabric with <= 8B which might trigger a fabric corner case hang issue. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7500ef6eb5..a80ecdca84 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1017,7 +1017,6 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } -#ifdef RTE_LIBRTE_BBDEV_DEBUG static inline bool is_acc100(struct acc_queue *q) @@ -1030,7 +1029,6 @@ validate_op_required(struct acc_queue *q) { return is_acc100(q); } -#endif /* Fill in a frame control word for LDPC decoding. */ static inline void @@ -1355,12 +1353,28 @@ acc100_dma_fill_blk_type_in(struct acc_dma_req_desc *desc, return next_triplet; } +/* May need to pad LDPC Encoder input to avoid small beat for ACC100. */ +static inline uint16_t +pad_le_in(uint16_t blen, struct acc_queue *q) +{ + uint16_t last_beat; + + if (!is_acc100(q)) + return blen; + + last_beat = blen % 64; + if ((last_beat > 0) && (last_beat <= 8)) + blen += 8; + + return blen; +} + static inline int acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, struct acc_dma_req_desc *desc, struct rte_mbuf **input, struct rte_mbuf *output, uint32_t *in_offset, uint32_t *out_offset, uint32_t *out_length, - uint32_t *mbuf_total_left, uint32_t *seg_total_left) + uint32_t *mbuf_total_left, uint32_t *seg_total_left, struct acc_queue *q) { int next_triplet = 1; /* FCW already done */ uint16_t K, in_length_in_bits, in_length_in_bytes; @@ -1384,8 +1398,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - in_length_in_bytes, - seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -2035,7 +2048,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, acc_header_init(&desc->req); desc->req.numCBs = num; - in_length_in_bytes = ops[0]->ldpc_enc.input.data->data_len; + in_length_in_bytes = pad_le_in(ops[0]->ldpc_enc.input.data->data_len, q); out_length = (enc->cb_params.e + 7) >> 3; desc->req.m2dlen = 1 + num; desc->req.d2mlen = num; @@ -2102,7 +2115,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, ret = acc100_dma_desc_le_fill(op, &desc->req, &input, output, &in_offset, &out_offset, &out_length, &mbuf_total_left, - &seg_total_left); + &seg_total_left, q); if (unlikely(ret < 0)) return ret;