From patchwork Wed Oct 19 00:39:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118452 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11DC2A0560; Tue, 18 Oct 2022 18:44:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D8EB742B90; Tue, 18 Oct 2022 18:43:07 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 17844427F9 for ; Tue, 18 Oct 2022 18:42:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111377; x=1697647377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4Gza2lgLVnc+AKnEvMYkxN5QsSl4HGtPC4UGcnVbpwA=; b=CD0gKSWM/oaqDAXW/sF2ZeLwQiGqrFQTjSoYBpFqLXBRgzKtu2QdzUKA vjnslVZwdihGS7x9CBuSj3hIcgbTgIcFG/AGtu/zEj84EhI/ojpGJCoC8 rrgqY2VVZpbCfvxsruIAGumk+UoRPILh76V3k/Wa5ZvP3rBts8N5snbio WpDVtjbQgbDdJ39X7TKzlDuJrnDghJlnQiSmj0rVon3S+ND1WI/CVOKAU Rm0/qtP2BMXRr1p57Vcc70u9OMneLfuDOAZzjGJLZjkHlPTxqP9G1Z8CF S5gpqlc2SqgATAPjki3sCpzE+OSBtipw8pL9xufKrRciuzHBJdYnmnvR4 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192094" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192094" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836093" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836093" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:55 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 17/30] baseband/acc100: add HARQ index helper function Date: Tue, 18 Oct 2022 17:39:05 -0700 Message-Id: <20221019003918.257506-18-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor code to use the HARQ index helper function and make harq_idx uint32. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++-------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 0921e9a44d..d0c98ced32 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1050,7 +1050,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, union acc_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; - uint16_t harq_index; + uint32_t harq_index; uint32_t l; bool harq_prun = false; uint32_t max_hc_in; @@ -1098,8 +1098,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); - harq_index = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ harq_prun = ((op->ldpc_dec.harq_combined_output.offset % @@ -1777,20 +1776,17 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, *h_out_length = desc->data_ptrs[next_triplet].blen; next_triplet++; - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { - desc->data_ptrs[next_triplet].address = - op->ldpc_dec.harq_combined_output.offset; + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + struct rte_bbdev_dec_op *prev_op; + uint32_t harq_idx, prev_harq_idx; + desc->data_ptrs[next_triplet].address = op->ldpc_dec.harq_combined_output.offset; /* Adjust based on previous operation */ - struct rte_bbdev_dec_op *prev_op = desc->op_addr; + prev_op = desc->op_addr; op->ldpc_dec.harq_combined_output.length = prev_op->ldpc_dec.harq_combined_output.length; - int16_t hq_idx = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; - int16_t prev_hq_idx = - prev_op->ldpc_dec.harq_combined_output.offset - / ACC_HARQ_OFFSET; - harq_layout[hq_idx].val = harq_layout[prev_hq_idx].val; + harq_idx = hq_index(op->ldpc_dec.harq_combined_output.offset); + prev_harq_idx = hq_index(prev_op->ldpc_dec.harq_combined_output.offset); + harq_layout[harq_idx].val = harq_layout[prev_harq_idx].val; #ifndef ACC100_EXT_MEM struct rte_bbdev_op_data ho = op->ldpc_dec.harq_combined_output; @@ -2534,6 +2530,9 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *hq_output_head, *hq_output; uint16_t harq_dma_length_in, harq_dma_length_out; uint16_t harq_in_length = op->ldpc_dec.harq_combined_input.length; + bool ddr_mem_in; + union acc_harq_layout_data *harq_layout; + uint32_t harq_index; if (harq_in_length == 0) { rte_bbdev_log(ERR, "Loopback of invalid null size\n"); @@ -2553,13 +2552,12 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, } harq_dma_length_out = harq_dma_length_in; - bool ddr_mem_in = check_bit(op->ldpc_dec.op_flags, + ddr_mem_in = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE); - union acc_harq_layout_data *harq_layout = q->d->harq_layout; - uint16_t harq_index = (ddr_mem_in ? + harq_layout = q->d->harq_layout; + harq_index = hq_index(ddr_mem_in ? op->ldpc_dec.harq_combined_input.offset : - op->ldpc_dec.harq_combined_output.offset) - / ACC_HARQ_OFFSET; + op->ldpc_dec.harq_combined_output.offset); desc = acc_desc(q, total_enqueued_cbs); fcw = &desc->req.fcw_ld;