From: Hanumanth Pothula <hpothula@marvell.com>
Presently, HW is programmed only to receive packets from LPB pool.
Making all packets received from LPB pool.
But, CNXK HW supports two pools,
- SPB -> packets with smaller size (less than 4K)
- LPB -> packets with bigger size (greater than 4K)
Patch enables multiple mempool capability, pool is selected based
on the packet's length. So, basically, PMD programs HW for receiving
packets from both SPB and LPB pools based on the packet's length.
This is achieved by enabling rx multiple mempool offload,
RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL. This allows the application to send
more than one pool(in our case two) to the driver, with different
segment(packet) lengths, which helps the driver to configure both
pools based on segment lengths.
This is often useful for saving the memory where the application
can create a different pool to steer the specific size of the
packet, thus enabling effective use of memory.
Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
---
drivers/net/cnxk/cnxk_ethdev.c | 84 ++++++++++++++++++++++++++----
drivers/net/cnxk/cnxk_ethdev.h | 2 +
drivers/net/cnxk/cnxk_ethdev_ops.c | 3 ++
3 files changed, 80 insertions(+), 9 deletions(-)
@@ -541,6 +541,58 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
plt_free(txq_sp);
}
+static int
+cnxk_nix_process_rx_conf(const struct rte_eth_rxconf *rx_conf,
+ struct rte_mempool **lpb_pool,
+ struct rte_mempool **spb_pool)
+{
+ struct rte_mempool *pool0;
+ struct rte_mempool *pool1;
+ struct rte_mempool **mp = rx_conf->rx_mempools;
+ const char *platform_ops;
+ struct rte_mempool_ops *ops;
+
+ if (*lpb_pool ||
+ rx_conf->rx_nmempool != CNXK_NIX_NUM_POOLS_MAX) {
+ plt_err("invalid arguments");
+ return -EINVAL;
+ }
+
+ if (mp == NULL || mp[0] == NULL || mp[1] == NULL) {
+ plt_err("invalid memory pools\n");
+ return -EINVAL;
+ }
+
+ pool0 = mp[0];
+ pool1 = mp[1];
+
+ if (pool0->elt_size > pool1->elt_size) {
+ *lpb_pool = pool0;
+ *spb_pool = pool1;
+
+ } else {
+ *lpb_pool = pool1;
+ *spb_pool = pool0;
+ }
+
+ if ((*spb_pool)->pool_id == 0) {
+ plt_err("Invalid pool_id");
+ return -EINVAL;
+ }
+
+ platform_ops = rte_mbuf_platform_mempool_ops();
+ ops = rte_mempool_get_ops((*spb_pool)->ops_index);
+ if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
+ plt_err("mempool ops should be of cnxk_npa type");
+ return -EINVAL;
+ }
+
+ plt_info("spb_pool:%s lpb_pool:%s lpb_len:%u spb_len:%u\n", (*spb_pool)->name,
+ (*lpb_pool)->name, (*lpb_pool)->elt_size, (*spb_pool)->elt_size);
+
+ return 0;
+}
+
int
cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
uint32_t nb_desc, uint16_t fp_rx_q_sz,
@@ -557,6 +609,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
uint16_t first_skip;
int rc = -EINVAL;
size_t rxq_sz;
+ struct rte_mempool *lpb_pool = mp;
+ struct rte_mempool *spb_pool = NULL;
/* Sanity checks */
if (rx_conf->rx_deferred_start == 1) {
@@ -564,15 +618,21 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
goto fail;
}
+ if (rx_conf->rx_nmempool > 0) {
+ rc = cnxk_nix_process_rx_conf(rx_conf, &lpb_pool, &spb_pool);
+ if (rc)
+ goto fail;
+ }
+
platform_ops = rte_mbuf_platform_mempool_ops();
/* This driver needs cnxk_npa mempool ops to work */
- ops = rte_mempool_get_ops(mp->ops_index);
+ ops = rte_mempool_get_ops(lpb_pool->ops_index);
if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
plt_err("mempool ops should be of cnxk_npa type");
goto fail;
}
- if (mp->pool_id == 0) {
+ if (lpb_pool->pool_id == 0) {
plt_err("Invalid pool_id");
goto fail;
}
@@ -589,13 +649,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
/* Its a no-op when inline device is not used */
if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
- roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+ roc_nix_inl_dev_xaq_realloc(lpb_pool->pool_id);
/* Increase CQ size to Aura size to avoid CQ overflow and
* then CPT buffer leak.
*/
if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
- nb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc);
+ nb_desc = nix_inl_cq_sz_clamp_up(nix, lpb_pool, nb_desc);
/* Setup ROC CQ */
cq = &dev->cqs[qid];
@@ -611,17 +671,17 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
rq = &dev->rqs[qid];
rq->qid = qid;
rq->cqid = cq->qid;
- rq->aura_handle = mp->pool_id;
+ rq->aura_handle = lpb_pool->pool_id;
rq->flow_tag_width = 32;
rq->sso_ena = false;
/* Calculate first mbuf skip */
first_skip = (sizeof(struct rte_mbuf));
first_skip += RTE_PKTMBUF_HEADROOM;
- first_skip += rte_pktmbuf_priv_size(mp);
+ first_skip += rte_pktmbuf_priv_size(lpb_pool);
rq->first_skip = first_skip;
rq->later_skip = sizeof(struct rte_mbuf);
- rq->lpb_size = mp->elt_size;
+ rq->lpb_size = lpb_pool->elt_size;
if (roc_errata_nix_no_meta_aura())
rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
@@ -629,6 +689,12 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
if (roc_nix_inl_inb_is_enabled(nix))
rq->ipsech_ena = true;
+ if (spb_pool) {
+ rq->spb_ena = 1;
+ rq->spb_aura_handle = spb_pool->pool_id;
+ rq->spb_size = spb_pool->elt_size;
+ }
+
rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
if (rc) {
plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
@@ -651,7 +717,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
/* Queue config should reflect global offloads */
rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
rxq_sp->qconf.nb_desc = nb_desc;
- rxq_sp->qconf.mp = mp;
+ rxq_sp->qconf.mp = lpb_pool;
rxq_sp->tc = 0;
rxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL ||
dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE);
@@ -670,7 +736,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
goto free_mem;
}
- plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
+ plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, lpb_pool->name, nb_desc,
cq->nb_desc);
/* Store start of fast path area */
@@ -44,6 +44,8 @@
#define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
/* Max supported SQB count */
#define CNXK_NIX_TX_MAX_SQB 512
+/* LPB & SPB */
+#define CNXK_NIX_NUM_POOLS_MAX 2
/* If PTP is enabled additional SEND MEM DESC is required which
* takes 2 words, hence max 7 iova address are possible
@@ -69,6 +69,9 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP |
RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
+ devinfo->max_rx_mempools = CNXK_NIX_NUM_POOLS_MAX;
+
return 0;
}