diff mbox series

[v2] regexdev: add maximum number of mbuf segments field

Message ID 20221007080422.280482-1-ggribbon@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers show
Series [v2] regexdev: add maximum number of mbuf segments field | expand

Checks

Context Check Description
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/github-robot: build success github build: passed
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/checkpatch success coding style OK

Commit Message

Gerry Gribbon Oct. 7, 2022, 8:04 a.m. UTC
Allows application to query maximum number of mbuf segments that can
be chained together.

Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
v2:
* Moved max_num_mbuf_segs field in the sparse rte_regexdev_info
  struct to reuse an existing hole.
* Renamed max_num_mbuf_segs to max_segs.

 drivers/regex/mlx5/mlx5_regex.h          |  1 +
 drivers/regex/mlx5/mlx5_regex_fastpath.c | 43 ++++++++++++++++++++++++
 drivers/regex/mlx5/mlx5_rxp.c            |  1 +
 lib/regexdev/rte_regexdev.h              |  2 ++
 4 files changed, 47 insertions(+)

Comments

Thomas Monjalon Oct. 9, 2022, 12:56 p.m. UTC | #1
07/10/2022 10:04, Gerry Gribbon:
> Allows application to query maximum number of mbuf segments that can
> be chained together.
> 
> Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 89495301ac..98fe95b781 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -94,4 +94,5 @@  uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops);
 uint16_t mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id,
 		       struct rte_regex_ops **ops, uint16_t nb_ops);
+uint16_t mlx5_regexdev_max_segs_get(void);
 #endif /* MLX5_REGEX_H */
diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c
index 0a8c83fe14..d6c747aeae 100644
--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c
+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c
@@ -41,6 +41,39 @@ 
 /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */
 #define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \
 	(((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2))
+#ifdef RTE_LIBRTE_MLX5_DEBUG
+#define MLX5_REGEX_DEBUG 0
+#endif
+#ifdef HAVE_MLX5_UMR_IMKEY
+static uint16_t max_nb_segs = MLX5_REGEX_MAX_KLM_NUM;
+#else
+static uint16_t max_nb_segs = 1;
+#endif
+
+uint16_t
+mlx5_regexdev_max_segs_get(void)
+{
+	return max_nb_segs;
+}
+
+#ifdef MLX5_REGEX_DEBUG
+static inline uint16_t
+validate_ops(struct rte_regex_ops **ops, uint16_t nb_ops)
+{
+	uint16_t nb_left = nb_ops;
+	struct rte_mbuf *mbuf;
+
+	while (nb_left--) {
+		mbuf = ops[nb_left]->mbuf;
+		if ((mbuf->pkt_len > MLX5_RXP_MAX_JOB_LENGTH) ||
+		    (mbuf->nb_segs > max_nb_segs)) {
+			DRV_LOG(ERR, "Failed to validate regex ops");
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
 
 static inline uint32_t
 qp_size_get(struct mlx5_regex_hw_qp *qp)
@@ -375,6 +408,11 @@  mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id,
 	struct mlx5_regex_hw_qp *qp_obj;
 	size_t hw_qpid, nb_left = nb_ops, nb_desc;
 
+#ifdef MLX5_REGEX_DEBUG
+	if (validate_ops(ops, nb_ops))
+		return 0;
+#endif
+
 	while ((hw_qpid = ffs(queue->free_qps))) {
 		hw_qpid--; /* ffs returns 1 for bit 0 */
 		qp_obj = &queue->qps[hw_qpid];
@@ -409,6 +447,11 @@  mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,
 	struct mlx5_regex_hw_qp *qp_obj;
 	size_t hw_qpid, job_id, i = 0;
 
+#ifdef MLX5_REGEX_DEBUG
+	if (validate_ops(ops, nb_ops))
+		return 0;
+#endif
+
 	while ((hw_qpid = ffs(queue->free_qps))) {
 		hw_qpid--; /* ffs returns 1 for bit 0 */
 		qp_obj = &queue->qps[hw_qpid];
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index ed3af15e40..eadc7fe603 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -45,6 +45,7 @@  mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
 			      RTE_REGEXDEV_CAPA_QUEUE_PAIR_OOS_F;
 	info->rule_flags = 0;
 	info->max_queue_pairs = UINT16_MAX;
+	info->max_segs = mlx5_regexdev_max_segs_get();
 	return 0;
 }
 
diff --git a/lib/regexdev/rte_regexdev.h b/lib/regexdev/rte_regexdev.h
index 6061e648b1..9473c6bb4c 100644
--- a/lib/regexdev/rte_regexdev.h
+++ b/lib/regexdev/rte_regexdev.h
@@ -612,6 +612,8 @@  struct rte_regexdev_info {
 	/**< Maximum payload size for a pattern match request or scan.
 	 * @see RTE_REGEXDEV_CFG_CROSS_BUFFER_SCAN_F
 	 */
+	uint16_t max_segs;
+	/**< Maximum number of mbuf segments that can be chained together. */
 	uint32_t max_rules_per_group;
 	/**< Maximum rules supported per group by this device. */
 	uint16_t max_groups;