From patchwork Thu Oct 6 11:01:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117455 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A0D2A00C2; Thu, 6 Oct 2022 13:02:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C4DD42C2A; Thu, 6 Oct 2022 13:02:27 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) by mails.dpdk.org (Postfix) with ESMTP id 80A2A42C29 for ; Thu, 6 Oct 2022 13:02:25 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=J8sC3TIZ+d3zHxKRgE/DvdKG3qD9PDEeJrNS/51UT1v8X65ahYby8zLM4TSHbmIf2VkujG4u0Q0QV554c9NGnn4nYqWzjCho2hO3kRKFQ0nfaI8BT1Izmcliq4fJKJN45uOFTbfeAiNGe+1j3ICp4o4ShFKJ8BxSiiRMLJxrX4tU9rT5IvyeRU3SACIz5qswxkKCpv95ckY1WcOioishd2NdANjd/pPFRgStNvACdtkefN/88/byO30vN04kVKQcdOnbWoHRLji4cdoyKYlxI1eyNNYZRsoykIG0T/P/JXpilchXlfTovzQcjZqVBMHGhztoi9rb3eAXLNewb+MNZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nqa6e73nlLKek/zoPRxKR44O9u+smjikRMB8IIS2kFM=; b=Qx1vpITrR6KsFuAlv38xnq9GbboGPz8n2PIvdm8z68MYMjxZL78dTFA2nM3tXYU3E2B9Q2s2aoXf3WIjemz6rQ43ro3SizLMT9KnvGHR8ybxUOipzM4edgAqUci0EYEbC4pih9o3HTvwxTMv70cClvyBYxhQgEB+G0mGZu7PqfOj8bREHBh6gMIRz35p8jReGhLfjqxOja+WlsdOTF7LLiSdTy5Xve15aWv7K7AYvZf+HGuztov2mCSzqhptuYK34do1E62sp74/TUco+8xLkHaOLkJvQ9FWlZZbeK3i3FU9kcXkO5G6yz8bho2ttCYL8eSVebLg70OyjqOTwPRoVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Nqa6e73nlLKek/zoPRxKR44O9u+smjikRMB8IIS2kFM=; b=Aq+rvI9wxCz2WNTne7E6JGwnfG6BZEzmYNbwrvv+HNrynrcslK49aKJujObEnXNVW6sGt1OadrMSbi8G+MJlOkQ8vfQN2QoHtwOzIoHamdPdSVCXQubRV5BC81yLPijMtBFzA25C6JNyNCp30399CjeCO3u6iM6hN9RV7bzZd6xb0inxqzhqHEtirAK6i23XTnmW0pjebjYKWJAdeq1z3SppUHc4+CRQkLGnXFb8AHaS88iNXuSO2oCgNb31OOOW7wsiqDamgikPbOgCIHi3c5WDLjhhtahsioL8eu2Zecs7zNXcsd7QKa7zxKWPwxC5VECb8fiZ4DrDK3zuDbZ80g== Received: from BN0PR03CA0005.namprd03.prod.outlook.com (2603:10b6:408:e6::10) by LV2PR12MB5967.namprd12.prod.outlook.com (2603:10b6:408:170::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.28; Thu, 6 Oct 2022 11:02:23 +0000 Received: from BN8NAM11FT079.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e6:cafe::ed) by BN0PR03CA0005.outlook.office365.com (2603:10b6:408:e6::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT079.mail.protection.outlook.com (10.13.177.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:02:06 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:02:05 -0700 From: Dariusz Sosnowski To: Aman Singh , Yuying Zhang CC: Subject: [PATCH v2 7/8] app/testpmd: add hairpin queues memory modes Date: Thu, 6 Oct 2022 11:01:04 +0000 Message-ID: <20221006110105.2986966-8-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT079:EE_|LV2PR12MB5967:EE_ X-MS-Office365-Filtering-Correlation-Id: a7847205-e7d8-47b2-8296-08daa78a3f4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 63XGb6otXnSsOkGkzEdTnUNwJAp2g1VDw4hltHQJ9odwE7GVAkoiwrlQl90TNri3uw/abd5mrLwxaRePOhm3111zV9U6fxm9e/1CDC+QYlV8TTgopk4iBq7M7yBLvucJK7py9ILC6L0uQJoXLyocg4agieYDMqEOTPNd39ZlOD4Rkns0ey8Cnfo0aiHLpdbEluYCKl+65i2dAObG9nRDcUzmgDEhGzA2QuXynzuGIg1JxZc0U/YuHFtgIdt7ESL3auOM+YmCDpdbtLGaJM4ef+ah/MqsyshsYLYNUXiCCiRwucbwqqoMCyUrpeewxyOJMp6twSRkNNNbdJMnn/alrvu0Nb4+vUwoZxK9fucs4/blBItFoT+iOIrLbaCIBRm3iZFS8FSyD6yQJDC6l98kLC1yAEIRzWmqISapbf08Eyg5Pcp8jMk4nm1I3QOnrc8Yypmi3LtsLTNEyEH8paayXneqY5JAM5g7+o2/9vtWqlAa5gwy8jtAUAmBayQTNeecYg/aeQ6WHQDaeE3TXuOqChdxZXvoTltD0mBnIPEYxfWjKNJhX4odE0vMSSnqNcH40ibapYZB3KcvDDYO6c6TOOjCCka10eELe5r5X2dY+dqeEt3KcCS+l5K74QsZpE1F69ArwmjsZoMON1s0LlapeFI3USVK0OH7KJ3v2E1qzYCf7LqkEhXqfRkEq8CkYDwz+5qk7D3G5LKcfCkRJk7J/8fSY3iPWTJ7Kf26dF7QThc1zTjOqBgdsMm6mKDbfeFsO3PpmPL2QTjq639D6dAZDhpQnsseBqI4fqVo/T45904= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(2906002)(8936002)(70206006)(316002)(36756003)(8676002)(478600001)(41300700001)(86362001)(70586007)(4326008)(5660300002)(110136005)(36860700001)(55016003)(16526019)(83380400001)(356005)(26005)(2616005)(1076003)(47076005)(6286002)(40460700003)(186003)(336012)(7636003)(82740400003)(7696005)(40480700001)(426003)(82310400005)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:23.3750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7847205-e7d8-47b2-8296-08daa78a3f4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5967 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends hairpin-mode command line option of test-pmd application with an ability to configure whether Rx/Tx hairpin queue should use locked device memory or RTE memory. For purposes of this configurations the following bits of 32 bit hairpin-mode are reserved: - Bit 8 - If set, then force_memory flag will be set for hairpin RX queue. - Bit 9 - If set, then force_memory flag will be set for hairpin TX queue. - Bits 12-15 - Memory options for hairpin Rx queue: - Bit 12 - If set, then use_locked_device_memory will be set. - Bit 13 - If set, then use_rte_memory will be set. - Bit 14 - Reserved for future use. - Bit 15 - Reserved for future use. - Bits 16-19 - Memory options for hairpin Tx queue: - Bit 16 - If set, then use_locked_device_memory will be set. - Bit 17 - If set, then use_rte_memory will be set. - Bit 18 - Reserved for future use. - Bit 19 - Reserved for future use. Signed-off-by: Dariusz Sosnowski --- app/test-pmd/parameters.c | 2 +- app/test-pmd/testpmd.c | 24 +++++++++++++++++++++++- app/test-pmd/testpmd.h | 2 +- doc/guides/testpmd_app_ug/run_app.rst | 10 ++++++++-- 4 files changed, 33 insertions(+), 5 deletions(-) diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index 1024b5419c..14752f9571 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -1085,7 +1085,7 @@ launch_args_parse(int argc, char** argv) if (errno != 0 || end == optarg) rte_exit(EXIT_FAILURE, "hairpin mode invalid\n"); else - hairpin_mode = (uint16_t)n; + hairpin_mode = (uint32_t)n; } if (!strcmp(lgopts[opt_idx].name, "burst")) { n = atoi(optarg); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index 39ee3d331d..bb1c901742 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -409,7 +409,7 @@ bool setup_on_probe_event = true; uint8_t clear_ptypes = true; /* Hairpin ports configuration mode. */ -uint16_t hairpin_mode; +uint32_t hairpin_mode; /* Pretty printing of ethdev events */ static const char * const eth_event_desc[] = { @@ -2519,6 +2519,16 @@ port_is_started(portid_t port_id) return 1; } +#define HAIRPIN_MODE_RX_FORCE_MEMORY RTE_BIT32(8) +#define HAIRPIN_MODE_TX_FORCE_MEMORY RTE_BIT32(9) + +#define HAIRPIN_MODE_RX_LOCKED_MEMORY RTE_BIT32(12) +#define HAIRPIN_MODE_RX_RTE_MEMORY RTE_BIT32(13) + +#define HAIRPIN_MODE_TX_LOCKED_MEMORY RTE_BIT32(16) +#define HAIRPIN_MODE_TX_RTE_MEMORY RTE_BIT32(17) + + /* Configure the Rx and Tx hairpin queues for the selected port. */ static int setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) @@ -2534,6 +2544,12 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) uint16_t peer_tx_port = pi; uint32_t manual = 1; uint32_t tx_exp = hairpin_mode & 0x10; + uint32_t rx_force_memory = hairpin_mode & HAIRPIN_MODE_RX_FORCE_MEMORY; + uint32_t rx_locked_memory = hairpin_mode & HAIRPIN_MODE_RX_LOCKED_MEMORY; + uint32_t rx_rte_memory = hairpin_mode & HAIRPIN_MODE_RX_RTE_MEMORY; + uint32_t tx_force_memory = hairpin_mode & HAIRPIN_MODE_TX_FORCE_MEMORY; + uint32_t tx_locked_memory = hairpin_mode & HAIRPIN_MODE_TX_LOCKED_MEMORY; + uint32_t tx_rte_memory = hairpin_mode & HAIRPIN_MODE_TX_RTE_MEMORY; if (!(hairpin_mode & 0xf)) { peer_rx_port = pi; @@ -2573,6 +2589,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_rxq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!tx_force_memory; + hairpin_conf.use_locked_device_memory = !!tx_locked_memory; + hairpin_conf.use_rte_memory = !!tx_rte_memory; diag = rte_eth_tx_hairpin_queue_setup (pi, qi, nb_txd, &hairpin_conf); i++; @@ -2596,6 +2615,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_txq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!rx_force_memory; + hairpin_conf.use_locked_device_memory = !!rx_locked_memory; + hairpin_conf.use_rte_memory = !!rx_rte_memory; diag = rte_eth_rx_hairpin_queue_setup (pi, qi, nb_rxd, &hairpin_conf); i++; diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index 627a42ce3b..2244c25e97 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -562,7 +562,7 @@ extern uint16_t stats_period; extern struct rte_eth_xstat_name *xstats_display; extern unsigned int xstats_display_num; -extern uint16_t hairpin_mode; +extern uint32_t hairpin_mode; #ifdef RTE_LIB_LATENCYSTATS extern uint8_t latencystats_enabled; diff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst index 8b41b960c8..abc3ec10a0 100644 --- a/doc/guides/testpmd_app_ug/run_app.rst +++ b/doc/guides/testpmd_app_ug/run_app.rst @@ -529,10 +529,16 @@ The command line options are: Enable display of RX and TX burst stats. -* ``--hairpin-mode=0xXX`` +* ``--hairpin-mode=0xXXXX`` - Set the hairpin port mode with bitmask, only valid when hairpin queues number is set:: + Set the hairpin port configuration with bitmask, only valid when hairpin queues number is set:: + bit 18 - hairpin TX queues will use RTE memory + bit 16 - hairpin TX queues will use locked device memory + bit 13 - hairpin RX queues will use RTE memory + bit 12 - hairpin RX queues will use locked device memory + bit 9 - force memory settings of hairpin TX queue + bit 8 - force memory settings of hairpin RX queue bit 4 - explicit Tx flow rule bit 1 - two hairpin ports paired bit 0 - two hairpin ports loop