This patch adds new HCA capability related to hairpin RQs. This new
capability, hairpin_data_buffer_locked, indicates whether HCA supports
locking data buffer of hairpin RQ in ICMC (Interconnect Context Memory
Cache).
Struct used to define RQ configuration (RQ context) is extended with
hairpin_data_buffer_type field, which configures data buffer for hairpin
RQ. It can take the following values:
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in unlocked memory in ICMC.
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in locked memory in ICMC.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++
drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++
drivers/common/mlx5/mlx5_prm.h | 12 ++++++++++--
3 files changed, 15 insertions(+), 2 deletions(-)
@@ -993,6 +993,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hairpin_sq_wqe_bb_size);
attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
hairpin_sq_wq_in_host_mem);
+ attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
+ hairpin_data_buffer_locked);
}
if (attr->log_min_stride_wqe_sz == 0)
attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
@@ -1293,6 +1295,7 @@ mlx5_devx_cmd_create_rq(void *ctx,
MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
+ MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
@@ -193,6 +193,7 @@ struct mlx5_hca_attr {
uint32_t log_max_hairpin_num_packets:5;
uint32_t hairpin_sq_wqe_bb_size:4;
uint32_t hairpin_sq_wq_in_host_mem:1;
+ uint32_t hairpin_data_buffer_locked:1;
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
@@ -313,6 +314,7 @@ struct mlx5_devx_create_rq_attr {
uint32_t state:4;
uint32_t flush_in_error_en:1;
uint32_t hairpin:1;
+ uint32_t hairpin_data_buffer_type:3;
uint32_t ts_format:2;
uint32_t user_index:24;
uint32_t cqn:24;
@@ -2024,7 +2024,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
u8 reserved_at_160[0x3];
u8 hairpin_sq_wqe_bb_size[0x5];
u8 hairpin_sq_wq_in_host_mem[0x1];
- u8 reserved_at_169[0x697];
+ u8 hairpin_data_buffer_locked[0x1];
+ u8 reserved_at_16a[0x696];
};
struct mlx5_ifc_esw_cap_bits {
@@ -2304,7 +2305,9 @@ struct mlx5_ifc_rqc_bits {
u8 reserved_at_c[0x1];
u8 flush_in_error_en[0x1];
u8 hairpin[0x1];
- u8 reserved_at_f[0xB];
+ u8 reserved_at_f[0x6];
+ u8 hairpin_data_buffer_type[0x3];
+ u8 reserved_at_a8[0x2];
u8 ts_format[0x02];
u8 reserved_at_1c[0x4];
u8 reserved_at_20[0x8];
@@ -2813,6 +2816,11 @@ enum {
MLX5_CQE_SIZE_128B = 0x1,
};
+enum {
+ MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0,
+ MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1,
+};
+
struct mlx5_ifc_cqc_bits {
u8 status[0x4];
u8 as_notify[0x1];