From patchwork Fri Sep 30 09:41:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 117206 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D181CA00C4; Fri, 30 Sep 2022 12:50:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 693E341140; Fri, 30 Sep 2022 12:50:18 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id B903D410F1 for ; Fri, 30 Sep 2022 12:50:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664535016; x=1696071016; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CWLC0JZmBjfD4m2jYCrk5wPN5Hy0S1JUXrPg+IFTmBE=; b=H+xErSd+KomupcQtx+2ncA2mhDtieuC/xEAuls5mviXphAbEosOm9WKB Fd7UpGBLbOMQZ66xaXgUgRn/zeaS3dgpmWXOXohWwVfJNGQS8fWIOrl8c Ny/vuzdyXZesZc2k5l8ZYLNVxKdc0z3BeGXVdpMrnY8AsVh+VHjJ+lOF9 rnPyu7hWiMNP+zNjCpqZv6vPhIvJTZhosd5t4Jc3/iM8Bz3CBBQvjiJWT 52vCKXFhuqSDRnnBLKxmdB6w3Fpuyz3wmBr8ba4O0D1a/f60FwfX5CK8E JEvHysj5FodDLQ8RLVlmRi8kFN9zz08ORJf2vok4JZ5AcbDPaw594zXuI g==; X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="388441587" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="388441587" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 03:50:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="685244898" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="685244898" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2022 03:50:15 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, Arek Kusztal Subject: [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm Date: Fri, 30 Sep 2022 10:41:07 +0100 Message-Id: <20220930094108.6406-2-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20220930094108.6406-1-arkadiuszx.kusztal@intel.com> References: <20220930094108.6406-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Added ShangMi 4 (SM4) encryption algorithms. Supported modes: ECB, CBC, CTR. Signed-off-by: Arek Kusztal --- doc/guides/cryptodevs/features/qat.ini | 3 +++ doc/guides/rel_notes/release_22_11.rst | 4 ++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 9 +++++++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 9 +++++++++ drivers/crypto/qat/qat_sym_session.c | 12 ++++++++++++ 5 files changed, 37 insertions(+) diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini index b9755a757e..edabc030d7 100644 --- a/doc/guides/cryptodevs/features/qat.ini +++ b/doc/guides/cryptodevs/features/qat.ini @@ -40,6 +40,9 @@ KASUMI F8 = Y AES DOCSIS BPI = Y DES DOCSIS BPI = Y ZUC EEA3 = Y +SM4 ECB = Y +SM4 CBC = Y +SM4 CTR = Y ; ; Supported authentication algorithms of the 'qat' crypto driver. ; diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index d6278f1ff0..42aba19af7 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -105,6 +105,10 @@ New Features Added ``RTE_CRYPTO_AUTH_SM3`` to the auth algorithm list in the cryptodev. +* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.** + + Added SM4 encryption algorithm to the QAT PMD. + Supported modes are ECB, CBC and CTR. Removed Items ------------- diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 2d5f10aeac..d1285cdbd4 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -131,6 +131,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = { CAP_RNG(key_size, 32, 32, 0), CAP_RNG(digest_size, 16, 16, 0), CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), + QAT_SYM_CIPHER_CAP(SM4_ECB, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)), + QAT_SYM_CIPHER_CAP(SM4_CBC, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_CIPHER_CAP(SM4_CTR, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index a9457d9278..efbbbda4b6 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -91,6 +91,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { CAP_RNG(key_size, 32, 32, 0), CAP_RNG(digest_size, 16, 16, 0), CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), + QAT_SYM_CIPHER_CAP(SM4_ECB, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)), + QAT_SYM_CIPHER_CAP(SM4_CBC, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_CIPHER_CAP(SM4_CTR, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 52b3455cf0..68a38aa69b 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -465,6 +465,18 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_XTS_MODE; break; + case RTE_CRYPTO_CIPHER_SM4_ECB: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; + case RTE_CRYPTO_CIPHER_SM4_CBC: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE; + break; + case RTE_CRYPTO_CIPHER_SM4_CTR: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; + break; case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_AES_ECB: case RTE_CRYPTO_CIPHER_AES_F8: