From patchwork Tue Sep 27 07:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 116958 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA82CA00C2; Tue, 27 Sep 2022 09:59:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E4EC410D0; Tue, 27 Sep 2022 09:59:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C693140696 for ; Tue, 27 Sep 2022 09:59:08 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28R491a8031941 for ; Tue, 27 Sep 2022 00:59:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=dwnaXbFO4pHopXmKPMzSwr28gmqOnkuk9hh2gyqDoGo=; b=NpFTwk1VOB2OR2NjI2uI/4QJ0WpJO94KIqtaVS6kdc6IarVfzjC0OYOyV3eZW4mCmCog ViLwKDksyq3Vat0fO7V+6zoUzVzHUvLefZJK+PL9glirZB8Kctx38TKVoywOxyMx84en LJL7bxX9oG5LWvYaKnBozJipAJCHqXeW4Jmuqu7J0QN1qv3eJSfwDZYeDWnvzjM2s9my P+M6XPOwjk+j8c3Ue/k/0ztWEmIwWQC/9HnnRrHBSDzOUt3YVb5+rMaA/37KeHezKjW1 nSdp6qWRyioxGbmQ6AATtetxZY5VP42XML7MSB0pBe+JBC8nY9EzzOlhI99vnTOWRehd YA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jucsq39jn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 27 Sep 2022 00:59:07 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Sep 2022 00:59:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 27 Sep 2022 00:59:06 -0700 Received: from localhost.localdomain (unknown [10.28.34.38]) by maili.marvell.com (Postfix) with ESMTP id 9FA0A3F7041; Tue, 27 Sep 2022 00:59:03 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: Anoob Joseph , Ankur Dwivedi , Tejasree Kondoj , Akhil Goyal , , Kiran Kumar K , "Gowrishankar Muthukrishnan" Subject: [v1] crypto/cnxk: add support for fixed point multiplication Date: Tue, 27 Sep 2022 13:29:00 +0530 Message-ID: <20220927075900.3667248-1-gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: vMd8lR0_i2RgqlfVcEBXREG16M45RPx7 X-Proofpoint-ORIG-GUID: vMd8lR0_i2RgqlfVcEBXREG16M45RPx7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-27_02,2022-09-22_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add fixed point multiplication for EC curve in CNXK. Signed-off-by: Kiran Kumar K Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Anoob Joseph --- drivers/common/cnxk/roc_ae.h | 1 + drivers/crypto/cnxk/cnxk_ae.h | 69 +++++++++++++++++++ .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 10 +++ 3 files changed, 80 insertions(+) diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h index 9c637d67ef..c972878eff 100644 --- a/drivers/common/cnxk/roc_ae.h +++ b/drivers/common/cnxk/roc_ae.h @@ -18,6 +18,7 @@ #define ROC_AE_MINOR_OP_ECDSA_SIGN 0x01 #define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02 #define ROC_AE_MINOR_OP_ECC_UMP 0x03 +#define ROC_AE_MINOR_OP_ECC_FPM 0x04 /** * Enumeration roc_ae_ec_id diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index 0562f72270..4a7ce0bf40 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -181,6 +181,7 @@ cnxk_ae_fill_session_parameters(struct cnxk_ae_sess *sess, case RTE_CRYPTO_ASYM_XFORM_ECDSA: /* Fall through */ case RTE_CRYPTO_ASYM_XFORM_ECPM: + case RTE_CRYPTO_ASYM_XFORM_ECFPM: ret = cnxk_ae_fill_ec_params(sess, xform); break; default: @@ -207,6 +208,7 @@ cnxk_ae_free_session_parameters(struct cnxk_ae_sess *sess) case RTE_CRYPTO_ASYM_XFORM_ECDSA: /* Fall through */ case RTE_CRYPTO_ASYM_XFORM_ECPM: + case RTE_CRYPTO_ASYM_XFORM_ECFPM: break; default: break; @@ -600,6 +602,64 @@ cnxk_ae_enqueue_ecdsa_op(struct rte_crypto_op *op, return 0; } +static __rte_always_inline int +cnxk_ae_ecfpm_prep(struct rte_crypto_ecpm_op_param *ecpm, + struct roc_ae_buf_ptr *meta_buf, uint64_t *fpm_iova, + struct roc_ae_ec_group *ec_grp, uint8_t curveid, + struct cpt_inst_s *inst) +{ + uint16_t scalar_align, p_align; + uint16_t dlen, prime_len; + uint64_t fpm_table_iova; + union cpt_inst_w4 w4; + uint8_t *dptr; + + prime_len = ec_grp->prime.length; + fpm_table_iova = (uint64_t)fpm_iova[curveid]; + + /* Input buffer */ + dptr = meta_buf->vaddr; + inst->dptr = (uintptr_t)dptr; + + p_align = RTE_ALIGN_CEIL(prime_len, 8); + scalar_align = RTE_ALIGN_CEIL(ecpm->scalar.length, 8); + + /* + * Set dlen = sum(ROUNDUP8(input point(x and y coordinates), prime, + * scalar length), + * Please note point length is equivalent to prime of the curve + */ + dlen = sizeof(fpm_table_iova) + 3 * p_align + scalar_align; + + memset(dptr, 0, dlen); + + *(uint64_t *)dptr = fpm_table_iova; + dptr += sizeof(fpm_table_iova); + + /* Copy scalar, prime */ + memcpy(dptr, ecpm->scalar.data, ecpm->scalar.length); + dptr += scalar_align; + memcpy(dptr, ec_grp->prime.data, ec_grp->prime.length); + dptr += p_align; + memcpy(dptr, ec_grp->consta.data, ec_grp->consta.length); + dptr += p_align; + memcpy(dptr, ec_grp->constb.data, ec_grp->constb.length); + dptr += p_align; + + /* Setup opcodes */ + w4.s.opcode_major = ROC_AE_MAJOR_OP_ECC; + w4.s.opcode_minor = ROC_AE_MINOR_OP_ECC_FPM; + + w4.s.param1 = curveid | (1 << 8); + w4.s.param2 = ecpm->scalar.length; + w4.s.dlen = dlen; + + inst->w4.u64 = w4.u64; + inst->rptr = (uintptr_t)dptr; + + return 0; +} + static __rte_always_inline int cnxk_ae_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm, struct roc_ae_buf_ptr *meta_buf, @@ -811,6 +871,14 @@ cnxk_ae_enqueue(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, if (unlikely(ret)) goto req_fail; break; + case RTE_CRYPTO_ASYM_XFORM_ECFPM: + ret = cnxk_ae_ecfpm_prep(&asym_op->ecpm, &meta_buf, + sess->cnxk_fpm_iova, + sess->ec_grp[sess->ec_ctx.curveid], + sess->ec_ctx.curveid, inst); + if (unlikely(ret)) + goto req_fail; + break; default: op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; ret = -EINVAL; @@ -845,6 +913,7 @@ cnxk_ae_post_process(struct rte_crypto_op *cop, struct cnxk_ae_sess *sess, sess->ec_grp); break; case RTE_CRYPTO_ASYM_XFORM_ECPM: + case RTE_CRYPTO_ASYM_XFORM_ECFPM: cnxk_ae_dequeue_ecpm_op(&op->ecpm, rptr, &sess->ec_ctx, sess->ec_grp); break; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index 705d67e91f..e32f476dd9 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -82,6 +82,16 @@ static const struct rte_cryptodev_capabilities caps_mul[] = { }, } }, + { /* ECFPM */ + .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, + {.asym = { + .xform_capa = { + .xform_type = RTE_CRYPTO_ASYM_XFORM_ECFPM, + .op_types = 0 + } + }, + } + }, }; static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {