From patchwork Tue Sep 27 07:32:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 116956 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06E2DA00C2; Tue, 27 Sep 2022 09:34:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D3F342B77; Tue, 27 Sep 2022 09:33:58 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id C277842B8F for ; Tue, 27 Sep 2022 09:33:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664264035; x=1695800035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rf6KLm9m1Xegj//2ancNQA9KOyziZJc0gvJuO1iSg40=; b=mWAAOgiLqyTIteTZ99+kgAwU5zYB2LBD9S1pH0g5uzyM3MT3cmM9IlpL qIO5H1iz7VwBcmfbrLE3VZTz0fcenqDqVIXO2a/dTYswkMeLrUG+io+o9 zoSXy3lMgfzCYX7KaOpPuWBPwcBAZOYGgD1sJ7HZ5rPxgFd7GwJkrI3t2 dVJcwvTnfvb7OFCt2zf9WXmsbtlJtVwIHtDj/3VTnXxZMX94BUVg9v8us jFZiFNyUKVGmY7zzdSP2qpXcbPbsscS7uQ1w3D8V0MlDY0pwRd5DNayfw Unw+7MdpxX+OIO8UHyui9XE5kX5wwLftsa4lyim4SXMJ8MP0w6REYRUGa w==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="298844158" X-IronPort-AV: E=Sophos;i="5.93,348,1654585200"; d="scan'208";a="298844158" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 00:33:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="866470214" X-IronPort-AV: E=Sophos;i="5.93,348,1654585200"; d="scan'208";a="866470214" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104]) by fmsmga006.fm.intel.com with ESMTP; 27 Sep 2022 00:33:53 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com Cc: ferruh.yigit@xilinx.com, dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com, bruce.richardson@intel.com, xueqin.lin@intel.com, junfeng.guo@intel.com Subject: [PATCH v4 8/9] net/gve: add support for dev info get and dev configure Date: Tue, 27 Sep 2022 15:32:54 +0800 Message-Id: <20220927073255.1803892-9-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927073255.1803892-1-junfeng.guo@intel.com> References: <20220923093829.3019525-2-junfeng.guo@intel.com> <20220927073255.1803892-1-junfeng.guo@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add dev_ops dev_infos_get. Complete dev_configure with RX offloads configuration. Signed-off-by: Xiaoyun Li Signed-off-by: Junfeng Guo --- doc/guides/nics/features/gve.ini | 1 + drivers/net/gve/gve_ethdev.c | 65 +++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/gve.ini b/doc/guides/nics/features/gve.ini index 38dc7024d6..cdc46b08a3 100644 --- a/doc/guides/nics/features/gve.ini +++ b/doc/guides/nics/features/gve.ini @@ -8,6 +8,7 @@ Speed capabilities = Y Link status = Y MTU update = Y TSO = Y +RSS hash = Y L4 checksum offload = Y Linux = Y x86-32 = Y diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c index 0aae447b9b..b9b8e51b02 100644 --- a/drivers/net/gve/gve_ethdev.c +++ b/drivers/net/gve/gve_ethdev.c @@ -91,8 +91,16 @@ gve_free_qpls(struct gve_priv *priv) } static int -gve_dev_configure(__rte_unused struct rte_eth_dev *dev) +gve_dev_configure(struct rte_eth_dev *dev) { + struct gve_priv *priv = dev->data->dev_private; + + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; + + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) + priv->enable_rsc = 1; + return 0; } @@ -266,6 +274,60 @@ gve_dev_close(struct rte_eth_dev *dev) return err; } +static int +gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct gve_priv *priv = dev->data->dev_private; + + dev_info->device = dev->device; + dev_info->max_mac_addrs = 1; + dev_info->max_rx_queues = priv->max_nb_rxq; + dev_info->max_tx_queues = priv->max_nb_txq; + dev_info->min_rx_bufsize = GVE_MIN_BUF_SIZE; + dev_info->max_rx_pktlen = GVE_MAX_RX_PKTLEN; + dev_info->max_mtu = RTE_ETHER_MTU; + dev_info->min_mtu = RTE_ETHER_MIN_MTU; + + dev_info->rx_offload_capa = 0; + dev_info->tx_offload_capa = + RTE_ETH_TX_OFFLOAD_MULTI_SEGS | + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_TSO; + + if (priv->queue_format == GVE_DQO_RDA_FORMAT) + dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = GVE_DEFAULT_RX_FREE_THRESH, + .rx_drop_en = 0, + .offloads = 0, + }; + + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = GVE_DEFAULT_TX_FREE_THRESH, + .offloads = 0, + }; + + dev_info->default_rxportconf.ring_size = priv->rx_desc_cnt; + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = priv->rx_desc_cnt, + .nb_min = priv->rx_desc_cnt, + .nb_align = 1, + }; + + dev_info->default_txportconf.ring_size = priv->tx_desc_cnt; + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = priv->tx_desc_cnt, + .nb_min = priv->tx_desc_cnt, + .nb_align = 1, + }; + + return 0; +} + static int gve_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { @@ -299,6 +361,7 @@ static const struct eth_dev_ops gve_eth_dev_ops = { .dev_start = gve_dev_start, .dev_stop = gve_dev_stop, .dev_close = gve_dev_close, + .dev_infos_get = gve_dev_info_get, .rx_queue_setup = gve_rx_queue_setup, .tx_queue_setup = gve_tx_queue_setup, .link_update = gve_link_update,