From patchwork Wed Sep 21 16:43:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 116586 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6B0FA00C3; Wed, 21 Sep 2022 18:43:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 58DA940691; Wed, 21 Sep 2022 18:43:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EF1204067C for ; Wed, 21 Sep 2022 18:43:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28LA54cP024593; Wed, 21 Sep 2022 09:43:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=SXtlsLlWVipYi99Jjri6fFHZTEjERTqwjsvK611I2gk=; b=OaWKvuj94gPM4mn7jpH0CyuXnOorwNCw+o+YWbb9tM/dU+IcuGvU1jaNWIW5WJbB+m62 iZvH0N97RknPTofCgSF+RvSx2hIlqLjhQz8rZtuuA0w9Jj78qHXVUfAoyoF6fTrm6Rdw lPnApuqBo0agM76XgVpfiDcsR5ZykBazxgNb/12U9cIR4xU2jo4jN0XbjGOJ6A12r/N4 ohlXo7r3qsM/ni2rLsl0rRxBlI4709MyewY8F3aZO6UVFgqs+cAIV1vUlDuYUbMbZpq8 CrGdKksuN/YT5wZeeRS/IXLx6vMuAcDl1bxSOlm9hKSxcC8ls5CJq4SmNszjfHZsqSYQ MA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jr0b71gc1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Sep 2022 09:43:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 21 Sep 2022 09:43:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 21 Sep 2022 09:43:49 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id BAD9A3F706D; Wed, 21 Sep 2022 09:43:44 -0700 (PDT) From: To: , Jay Jayatheerthan CC: , , , , , , , , , , , Pavan Nikhilesh Subject: [PATCH v2 1/3] eventdev: add element offset to event vector Date: Wed, 21 Sep 2022 22:13:40 +0530 Message-ID: <20220921164342.2174-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220816154932.10168-1-pbhagavatula@marvell.com> References: <20220816154932.10168-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NcjSy-5FtID1NfpWu0sN2192SpZkzmdF X-Proofpoint-GUID: NcjSy-5FtID1NfpWu0sN2192SpZkzmdF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-21_09,2022-09-20_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add `rte_event_vector:elem_offset:12` bit field event vector structure the bits are taken from `rte_event_vector::rsvd:15`. The element offset defines the offset into the vector array at which valid elements start. The valid elements count will be equal to `rte_event_vector::nb_elem`. Update Rx/Tx adapter SW implementation to use elem_offset. Signed-off-by: Pavan Nikhilesh Reviewed-by: Mattias Rönnblom --- v2 Changes: - Revert changes to definition of `rte_event_vector::nb_elem` lib/eventdev/rte_event_eth_rx_adapter.c | 1 + lib/eventdev/rte_event_eth_tx_adapter.c | 8 +++++--- lib/eventdev/rte_eventdev.h | 6 ++++-- 3 files changed, 10 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/lib/eventdev/rte_event_eth_rx_adapter.c b/lib/eventdev/rte_event_eth_rx_adapter.c index bf8741d2ea..bd72f9b845 100644 --- a/lib/eventdev/rte_event_eth_rx_adapter.c +++ b/lib/eventdev/rte_event_eth_rx_adapter.c @@ -855,6 +855,7 @@ rxa_init_vector(struct event_eth_rx_adapter *rx_adapter, vec->vector_ev->port = vec->port; vec->vector_ev->queue = vec->queue; vec->vector_ev->attr_valid = true; + vec->vector_ev->elem_offset = 0; TAILQ_INSERT_TAIL(&rx_adapter->vector_list, vec, next); } diff --git a/lib/eventdev/rte_event_eth_tx_adapter.c b/lib/eventdev/rte_event_eth_tx_adapter.c index b4b37f1cae..ccc7fffcce 100644 --- a/lib/eventdev/rte_event_eth_tx_adapter.c +++ b/lib/eventdev/rte_event_eth_tx_adapter.c @@ -524,16 +524,18 @@ txa_process_event_vector(struct txa_service_data *txa, queue = vec->queue; tqi = txa_service_queue(txa, port, queue); if (unlikely(tqi == NULL || !tqi->added)) { - rte_pktmbuf_free_bulk(mbufs, vec->nb_elem); + rte_pktmbuf_free_bulk(&mbufs[vec->elem_offset], + vec->nb_elem); rte_mempool_put(rte_mempool_from_obj(vec), vec); return 0; } for (i = 0; i < vec->nb_elem; i++) { nb_tx += rte_eth_tx_buffer(port, queue, tqi->tx_buf, - mbufs[i]); + mbufs[i + vec->elem_offset]); } } else { - for (i = 0; i < vec->nb_elem; i++) { + for (i = vec->elem_offset; i < vec->elem_offset + vec->nb_elem; + i++) { port = mbufs[i]->port; queue = rte_event_eth_tx_adapter_txq_get(mbufs[i]); tqi = txa_service_queue(txa, port, queue); diff --git a/lib/eventdev/rte_eventdev.h b/lib/eventdev/rte_eventdev.h index 6a6f6ea4c1..f9fd44604e 100644 --- a/lib/eventdev/rte_eventdev.h +++ b/lib/eventdev/rte_eventdev.h @@ -1060,8 +1060,10 @@ rte_event_dev_close(uint8_t dev_id); */ struct rte_event_vector { uint16_t nb_elem; - /**< Number of elements in this event vector. */ - uint16_t rsvd : 15; + /**< Number of elements valid in this event vector. */ + uint16_t elem_offset : 12; + /**< Offset into the vector array where valid elements start from. */ + uint16_t rsvd : 3; /**< Reserved for future use */ uint16_t attr_valid : 1; /**< Indicates that the below union attributes have valid information.