From patchwork Mon Sep 19 16:37:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 116444 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8802AA00C3; Mon, 19 Sep 2022 18:39:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA78742B73; Mon, 19 Sep 2022 18:39:42 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2057.outbound.protection.outlook.com [40.107.93.57]) by mails.dpdk.org (Postfix) with ESMTP id 5AE7C427F4 for ; Mon, 19 Sep 2022 18:39:41 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CbXw9G8ENFW72bT/q0xOB4M7DmYC0oVuve6rmFbnS6u/H7zhLOAx9dxOPMaOaf3hQSwruoRKIs8IhJN+4zDvIM/xkLKwqR1a3hZNJZ8r0vReB/KypKId/4hPIeyxm9HZaRu/1m2rmZKXDH5/bZ1XFrye8Mtyd0YKm+W+WrrNxZi/DhYyFA6oy3MhHSGgfFmGN4vY2h2X/7/j/FR/SricZvrf4sk5FRg7VLyt1exr+vduK2YvuDngrOt5ZNK7FN6hlBp+3doC0wwvujfuULxk0BuoCHGeLSzHi6c6SrFUswfj899CDYH58ykgbwim/VOGPojbLRnimm6iZgvSDS74qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sG7UflSqQLSgBDF5A+iD1DRFCi+rLXncl0/4QlHzksQ=; b=Qd99mEb5ri5DL+vl3ntitdYdCSUOCe3yG2iEM/ReMd38Sr6LlRRelMhre2lPSNrZH/N1O1DSNdBpigZrduJi4utXRDNVHzKdw3jQHF1l4diavoewh/pTc1yf159S+0dEyCoq826YndUbpF0RcEicIxaqVu6kVzncJJ4CyzCbtzhyXAydXxV1QsEiMdJNPx00C0Bl+OZEPbyFAn8BemBK8WSObCgzcdgV0Jfuwis95YPJNlyOWuOvd4WddT7UUygCpurFpf3sdaBwPW+6Ev/l1W5xg4qzJLljCeiqtUoQYYJNdMrK3Vg06kMp5kVDLpzvfwnTCFVrTiJhpsWUX9q+vA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sG7UflSqQLSgBDF5A+iD1DRFCi+rLXncl0/4QlHzksQ=; b=MbmzQZQy6+IwLm9jWi8U5Xh+YptVlX6wvdFnH6e7NjXQJASb5V7zhn6cGPFqc/KHw1+yroXZC8mo1GpNxztWFfUHcXaOORhnmFlGYddXkL5wvyDakdMN76ed5vEym5GU18JSJdhe3l6l+qZRwEqCfnKVe3ZoBKyQNqMAQbkT4R1C+3aSaXsLms6WT7tyQTrEJmvFz6FzF1iMLnzvukDWs2emNUQGi/wyMCXrEwyEx8/MevvK30bAKHhZfNNciuz6vRQjACPDWT0WKaJDgcpXVgs9iAcDr3e9Hv1u5t1XVR5a8lwnq92uU+C9dEFyKcNLmXCFhds5z8RQkMzn6oHwNw== Received: from DM6PR02CA0137.namprd02.prod.outlook.com (2603:10b6:5:1b4::39) by PH7PR12MB6657.namprd12.prod.outlook.com (2603:10b6:510:212::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.22; Mon, 19 Sep 2022 16:39:38 +0000 Received: from DM6NAM11FT095.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1b4:cafe::58) by DM6PR02CA0137.outlook.office365.com (2603:10b6:5:1b4::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.21 via Frontend Transport; Mon, 19 Sep 2022 16:39:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT095.mail.protection.outlook.com (10.13.172.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.12 via Frontend Transport; Mon, 19 Sep 2022 16:39:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Mon, 19 Sep 2022 09:39:26 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 19 Sep 2022 09:39:24 -0700 From: Dariusz Sosnowski To: Aman Singh , Yuying Zhang CC: Subject: [PATCH 6/7] app/testpmd: add hairpin queues memory modes Date: Mon, 19 Sep 2022 16:37:29 +0000 Message-ID: <20220919163731.1540454-7-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220919163731.1540454-1-dsosnowski@nvidia.com> References: <20220919163731.1540454-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT095:EE_|PH7PR12MB6657:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c38cd8c-ea5a-42a3-9208-08da9a5d8b5b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j08ZQ2GD9qQEjiydnef9YjRBEiYjtfdOFQTb8exBWoBJNtpvIFxNPhocMcE0eZQbUKB/QtgnXjK/LKVyz/IO5eCDTbgE+aMWynzU4neHTySLwYfSc+nvTQ0Ly/JE2KflwqA+25iCsyIZ6IEBCfsDstIlMfp70wZHbY/lo2WouoVrcXkPoYLIsrcBX8VI3WFQBJOjyHLcVazecEJb8A488it/hNmRdJI6UdSXq9axrm4/yO0QdIfl5f1dfiftGh/jbliDz2iSwUUq475Eue9pTv9SHr51aClC7kfZnc218q1rWVF4WpevdIbueO19oSlrWUoR2LPEy4SNP8C9KTuUSQF1+L8V9sqo2f9ELGdxx3hWnUpW76dzJvqPms2ymorE4FbH/BkLJom20Yw6sPyHCWymQiNRjcagbmWqnrXVaUYOiscaCa1VtTTZLymdiDXUaKyE1FcljU/fjpYgS9GJCyeXjp3Gh3D3ImxemqWmN9q0YX0nH7AHi/K8zqty4XB1PXWixUs2/d62NEvj626ZhvPxicYCZ9Fcuz1uUAl8h8Clbo9PB5PNqA5WkbIgXccbqg2gqg1tac66VxzK/Ynse82BussLqABGCFFVWTZgs45wnNTbYi2E7o93wDUQ+jvZwrQJNXju2J3qAuFuO6Tlc05e7+4U9+jx6JypDYObc8v3tfL4nlHeoJID7ApiZXI3CWSpO1Qunvc1ttT5tGVuZdwQBCPxSZ0Dkx+PdXqEB8qSzPFd7mcVueW758ov1t+Jzm9hWd9jmzdHEYmy5KaT0OPnqy9kGgrUoZAptbnu4Y8= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(26005)(70206006)(7636003)(82740400003)(82310400005)(4326008)(7696005)(6286002)(1076003)(8676002)(5660300002)(55016003)(47076005)(40480700001)(478600001)(2906002)(36756003)(83380400001)(336012)(110136005)(8936002)(40460700003)(36860700001)(316002)(2616005)(41300700001)(70586007)(356005)(16526019)(86362001)(186003)(426003)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:38.5610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c38cd8c-ea5a-42a3-9208-08da9a5d8b5b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT095.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6657 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends hairpin-mode command line option of test-pmd application with an ability to configure whether Rx/Tx hairpin queue should use locked device memory or RTE memory. For purposes of this configurations the following bits of 32 bit hairpin-mode are reserved: - Bit 8 - If set, then force_memory flag will be set for hairpin RX queue. - Bit 9 - If set, then force_memory flag will be set for hairpin TX queue. - Bits 12-15 - Memory options for hairpin Rx queue: - Bit 12 - If set, then use_locked_device_memory will be set. - Bit 13 - If set, then use_rte_memory will be set. - Bit 14 - Reserved for future use. - Bit 15 - Reserved for future use. - Bits 16-19 - Memory options for hairpin Tx queue: - Bit 16 - If set, then use_locked_device_memory will be set. - Bit 17 - If set, then use_rte_memory will be set. - Bit 18 - Reserved for future use. - Bit 19 - Reserved for future use. Signed-off-by: Dariusz Sosnowski --- app/test-pmd/parameters.c | 2 +- app/test-pmd/testpmd.c | 24 +++++++++++++++++++++++- app/test-pmd/testpmd.h | 2 +- doc/guides/testpmd_app_ug/run_app.rst | 10 ++++++++-- 4 files changed, 33 insertions(+), 5 deletions(-) diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index e3c9757f3f..662e6e4a36 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -1162,7 +1162,7 @@ launch_args_parse(int argc, char** argv) if (errno != 0 || end == optarg) rte_exit(EXIT_FAILURE, "hairpin mode invalid\n"); else - hairpin_mode = (uint16_t)n; + hairpin_mode = (uint32_t)n; } if (!strcmp(lgopts[opt_idx].name, "burst")) { n = atoi(optarg); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index addcbcac85..2fbd546073 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -409,7 +409,7 @@ bool setup_on_probe_event = true; uint8_t clear_ptypes = true; /* Hairpin ports configuration mode. */ -uint16_t hairpin_mode; +uint32_t hairpin_mode; /* Pretty printing of ethdev events */ static const char * const eth_event_desc[] = { @@ -2552,6 +2552,16 @@ port_is_started(portid_t port_id) return 1; } +#define HAIRPIN_MODE_RX_FORCE_MEMORY RTE_BIT32(8) +#define HAIRPIN_MODE_TX_FORCE_MEMORY RTE_BIT32(9) + +#define HAIRPIN_MODE_RX_LOCKED_MEMORY RTE_BIT32(12) +#define HAIRPIN_MODE_RX_RTE_MEMORY RTE_BIT32(13) + +#define HAIRPIN_MODE_TX_LOCKED_MEMORY RTE_BIT32(16) +#define HAIRPIN_MODE_TX_RTE_MEMORY RTE_BIT32(17) + + /* Configure the Rx and Tx hairpin queues for the selected port. */ static int setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) @@ -2567,6 +2577,12 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) uint16_t peer_tx_port = pi; uint32_t manual = 1; uint32_t tx_exp = hairpin_mode & 0x10; + uint32_t rx_force_memory = hairpin_mode & HAIRPIN_MODE_RX_FORCE_MEMORY; + uint32_t rx_locked_memory = hairpin_mode & HAIRPIN_MODE_RX_LOCKED_MEMORY; + uint32_t rx_rte_memory = hairpin_mode & HAIRPIN_MODE_RX_RTE_MEMORY; + uint32_t tx_force_memory = hairpin_mode & HAIRPIN_MODE_TX_FORCE_MEMORY; + uint32_t tx_locked_memory = hairpin_mode & HAIRPIN_MODE_TX_LOCKED_MEMORY; + uint32_t tx_rte_memory = hairpin_mode & HAIRPIN_MODE_TX_RTE_MEMORY; if (!(hairpin_mode & 0xf)) { peer_rx_port = pi; @@ -2606,6 +2622,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_rxq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!tx_force_memory; + hairpin_conf.use_locked_device_memory = !!tx_locked_memory; + hairpin_conf.use_rte_memory = !!tx_rte_memory; diag = rte_eth_tx_hairpin_queue_setup (pi, qi, nb_txd, &hairpin_conf); i++; @@ -2629,6 +2648,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_txq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!rx_force_memory; + hairpin_conf.use_locked_device_memory = !!rx_locked_memory; + hairpin_conf.use_rte_memory = !!rx_rte_memory; diag = rte_eth_rx_hairpin_queue_setup (pi, qi, nb_rxd, &hairpin_conf); i++; diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index fb2f5195d3..bc4d9788fa 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -542,7 +542,7 @@ extern uint16_t stats_period; extern struct rte_eth_xstat_name *xstats_display; extern unsigned int xstats_display_num; -extern uint16_t hairpin_mode; +extern uint32_t hairpin_mode; #ifdef RTE_LIB_LATENCYSTATS extern uint8_t latencystats_enabled; diff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst index 30edef07ea..c91c231094 100644 --- a/doc/guides/testpmd_app_ug/run_app.rst +++ b/doc/guides/testpmd_app_ug/run_app.rst @@ -556,10 +556,16 @@ The command line options are: Enable display of RX and TX burst stats. -* ``--hairpin-mode=0xXX`` +* ``--hairpin-mode=0xXXXX`` - Set the hairpin port mode with bitmask, only valid when hairpin queues number is set:: + Set the hairpin port configuration with bitmask, only valid when hairpin queues number is set:: + bit 18 - hairpin TX queues will use RTE memory + bit 16 - hairpin TX queues will use locked device memory + bit 13 - hairpin RX queues will use RTE memory + bit 12 - hairpin RX queues will use locked device memory + bit 9 - force memory settings of hairpin TX queue + bit 8 - force memory settings of hairpin RX queue bit 4 - explicit Tx flow rule bit 1 - two hairpin ports paired bit 0 - two hairpin ports loop