[2/7] common/mlx5: add hairpin SQ buffer type capabilities
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Commit Message
This patch extends HCA_CAP and SQ Context structs available in PRM. This
fields allow checking if NIC supports storing hairpin SQ's WQ buffer in
host memory and configuring such memory placement.
HCA capabilities are extended with the following fields:
- hairpin_sq_wq_in_host_mem - If set, then NIC supports using host
memory as a backing storage for hairpin SQ's WQ buffer.
- hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic
block.
SQ Context is extended with hairpin_wq_buffer_type which informs
NIC where SQ's WQ buffer will be stored. This field can take the
following values:
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be
stored in unlocked device memory.
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored
in host memory. Buffer is provided by PMD.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++
drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++
drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++++--
3 files changed, 21 insertions(+), 2 deletions(-)
Comments
> -----Original Message-----
> From: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Sent: Monday, September 19, 2022 19:37
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org
> Subject: [PATCH 2/7] common/mlx5: add hairpin SQ buffer type capabilities
>
> This patch extends HCA_CAP and SQ Context structs available in PRM. This
> fields allow checking if NIC supports storing hairpin SQ's WQ buffer in host
> memory and configuring such memory placement.
>
> HCA capabilities are extended with the following fields:
>
> - hairpin_sq_wq_in_host_mem - If set, then NIC supports using host memory as
> a backing storage for hairpin SQ's WQ buffer.
> - hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic
> block.
>
> SQ Context is extended with hairpin_wq_buffer_type which informs NIC where
> SQ's WQ buffer will be stored. This field can take the following values:
>
> - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be
> stored in unlocked device memory.
> - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored
> in host memory. Buffer is provided by PMD.
>
> Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
@@ -981,6 +981,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
}
attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
log_min_stride_wqe_sz);
+ attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
+ hairpin_sq_wqe_bb_size);
+ attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
+ hairpin_sq_wq_in_host_mem);
}
if (attr->log_min_stride_wqe_sz == 0)
attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
@@ -1698,6 +1702,7 @@ mlx5_devx_cmd_create_sq(void *ctx,
MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
+ MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
@@ -191,6 +191,8 @@ struct mlx5_hca_attr {
uint32_t log_max_hairpin_queues:5;
uint32_t log_max_hairpin_wq_data_sz:5;
uint32_t log_max_hairpin_num_packets:5;
+ uint32_t hairpin_sq_wqe_bb_size:4;
+ uint32_t hairpin_sq_wq_in_host_mem:1;
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
@@ -407,6 +409,7 @@ struct mlx5_devx_create_sq_attr {
uint32_t non_wire:1;
uint32_t static_sq_wq:1;
uint32_t ts_format:2;
+ uint32_t hairpin_wq_buffer_type:3;
uint32_t user_index:24;
uint32_t cqn:24;
uint32_t packet_pacing_rate_limit_index:16;
@@ -2020,7 +2020,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
u8 reserved_at_d8[0x3];
u8 log_max_conn_track_offload[0x5];
u8 reserved_at_e0[0x20]; /* End of DW7. */
- u8 reserved_at_100[0x700];
+ u8 reserved_at_100[0x60];
+ u8 reserved_at_160[0x3];
+ u8 hairpin_sq_wqe_bb_size[0x5];
+ u8 hairpin_sq_wq_in_host_mem[0x1];
+ u8 reserved_at_169[0x697];
};
struct mlx5_ifc_esw_cap_bits {
@@ -2673,6 +2677,11 @@ enum {
MLX5_SQC_STATE_ERR = 0x3,
};
+enum {
+ MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0,
+ MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1,
+};
+
struct mlx5_ifc_sqc_bits {
u8 rlky[0x1];
u8 cd_master[0x1];
@@ -2686,7 +2695,9 @@ struct mlx5_ifc_sqc_bits {
u8 hairpin[0x1];
u8 non_wire[0x1];
u8 static_sq_wq[0x1];
- u8 reserved_at_11[0x9];
+ u8 reserved_at_11[0x4];
+ u8 hairpin_wq_buffer_type[0x3];
+ u8 reserved_at_18[0x2];
u8 ts_format[0x02];
u8 reserved_at_1c[0x4];
u8 reserved_at_20[0x8];