diff mbox series

[v2,23/31] common/cnxk: add CQ limit associated with SQ

Message ID	20220905133228.818616-23-ndabilpuram@marvell.com (mailing list archive)
State	Superseded, archived
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com> CC: <jerinj@marvell.com>, <dev@dpdk.org>, Kommula Shiva Shankar <kshankar@marvell.com> Subject: [PATCH v2 23/31] common/cnxk: add CQ limit associated with SQ Date: Mon, 5 Sep 2022 19:02:20 +0530 Message-ID: <20220905133228.818616-23-ndabilpuram@marvell.com> In-Reply-To: <20220905133228.818616-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220905133228.818616-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	[v2,01/31] cnxk/net: add fc check in vector event Tx path \| [v2,01/31] cnxk/net: add fc check in vector event Tx path [v2,02/31] common/cnxk: fix part value for cn10k [v2,03/31] common/cnxk: add cn10ka A1 platform [v2,04/31] common/cnxk: update inbound inline IPsec config mailbox [v2,05/31] net/cnxk: fix missing fc wait for outbound path in vec mode [v2,06/31] common/cnxk: limit meta aura workaround to CN10K A0 [v2,07/31] common/cnxk: delay inline device RQ enable to dev start [v2,08/31] common/cnxk: reserve aura zero on cn10ka NPA [v2,09/31] common/cnxk: add support to set NPA buf type [v2,10/31] common/cnxk: update attributes to pools used by NIX [v2,11/31] common/cnxk: support zero aura for inline inbound meta [v2,12/31] net/cnxk: support for zero aura for inline meta [v2,13/31] common/cnxk: avoid the use of platform specific APIs [v2,14/31] net/cnxk: use full context IPsec structures in fp [v2,15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 [v2,16/31] common/cnxk: enable aging on CN10K platform [v2,17/31] common/cnxk: updated shaper profile with red algorithm [v2,18/31] common/cnxk: add 98xx A1 platform [v2,19/31] net/cnxk: enable additional ciphers for inline [v2,20/31] net/cnxk: enable 3des-cbc cipher capability [v2,21/31] net/cnxk: skip PFC configuration on LBK [v2,22/31] common/cnxk: add support for CPT second pass [v2,23/31] common/cnxk: add CQ limit associated with SQ [v2,24/31] common/cnxk: support Tx compl event via RQ to CQ mapping [v2,25/31] event/cnxk: wait for CPT fc on wqe path [v2,26/31] net/cnxk: limit port specific SA table size [v2,27/31] net/cnxk: add support for crypto cipher DES-CBC [v2,28/31] net/cnxk: Add support for crypto auth alg MD5 [v2,29/31] net/cnxk: enable esn and antireplay support [v2,30/31] common/cnxk: dump device basic info to file [v2,31/31] net/cnxk: dumps device private information

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Sept. 5, 2022, 1:32 p.m. UTC

  From: Kommula Shiva Shankar <kshankar@marvell.com>

Update CQ threshold limit associated with sq. This is
used when we need completions for packets that are successfully
transmitted.

Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>
---
 drivers/common/cnxk/roc_nix.h       | 1 +
 drivers/common/cnxk/roc_nix_queue.c | 2 ++
 2 files changed, 3 insertions(+)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index b17623076c..8869cf5169 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -346,6 +346,7 @@  struct roc_nix_sq {
 	uint32_t nb_desc;
 	uint16_t qid;
 	uint16_t cqid;
+	uint16_t cq_drop_thresh;
 	bool sso_ena;
 	bool cq_ena;
 	/* End of Input parameters */
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index b197de0a77..60303329cc 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -907,6 +907,7 @@  sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 	aq->sq.sso_ena = !!sq->sso_ena;
 	aq->sq.cq_ena = !!sq->cq_ena;
 	aq->sq.cq = sq->cqid;
+	aq->sq.cq_limit = sq->cq_drop_thresh;
 	if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
 		aq->sq.sqe_stype = NIX_STYPE_STP;
 	aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);
@@ -1024,6 +1025,7 @@  sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 	aq->sq.sso_ena = !!sq->sso_ena;
 	aq->sq.cq_ena = !!sq->cq_ena;
 	aq->sq.cq = sq->cqid;
+	aq->sq.cq_limit = sq->cq_drop_thresh;
 	if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
 		aq->sq.sqe_stype = NIX_STYPE_STP;
 	aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);