diff mbox series

[v2,18/31] common/cnxk: add 98xx A1 platform

Message ID	20220905133228.818616-18-ndabilpuram@marvell.com (mailing list archive)
State	Superseded, archived
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com> CC: <jerinj@marvell.com>, <dev@dpdk.org>, Harman Kalra <hkalra@marvell.com> Subject: [PATCH v2 18/31] common/cnxk: add 98xx A1 platform Date: Mon, 5 Sep 2022 19:02:15 +0530 Message-ID: <20220905133228.818616-18-ndabilpuram@marvell.com> In-Reply-To: <20220905133228.818616-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220905133228.818616-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	[v2,01/31] cnxk/net: add fc check in vector event Tx path \| [v2,01/31] cnxk/net: add fc check in vector event Tx path [v2,02/31] common/cnxk: fix part value for cn10k [v2,03/31] common/cnxk: add cn10ka A1 platform [v2,04/31] common/cnxk: update inbound inline IPsec config mailbox [v2,05/31] net/cnxk: fix missing fc wait for outbound path in vec mode [v2,06/31] common/cnxk: limit meta aura workaround to CN10K A0 [v2,07/31] common/cnxk: delay inline device RQ enable to dev start [v2,08/31] common/cnxk: reserve aura zero on cn10ka NPA [v2,09/31] common/cnxk: add support to set NPA buf type [v2,10/31] common/cnxk: update attributes to pools used by NIX [v2,11/31] common/cnxk: support zero aura for inline inbound meta [v2,12/31] net/cnxk: support for zero aura for inline meta [v2,13/31] common/cnxk: avoid the use of platform specific APIs [v2,14/31] net/cnxk: use full context IPsec structures in fp [v2,15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 [v2,16/31] common/cnxk: enable aging on CN10K platform [v2,17/31] common/cnxk: updated shaper profile with red algorithm [v2,18/31] common/cnxk: add 98xx A1 platform [v2,19/31] net/cnxk: enable additional ciphers for inline [v2,20/31] net/cnxk: enable 3des-cbc cipher capability [v2,21/31] net/cnxk: skip PFC configuration on LBK [v2,22/31] common/cnxk: add support for CPT second pass [v2,23/31] common/cnxk: add CQ limit associated with SQ [v2,24/31] common/cnxk: support Tx compl event via RQ to CQ mapping [v2,25/31] event/cnxk: wait for CPT fc on wqe path [v2,26/31] net/cnxk: limit port specific SA table size [v2,27/31] net/cnxk: add support for crypto cipher DES-CBC [v2,28/31] net/cnxk: Add support for crypto auth alg MD5 [v2,29/31] net/cnxk: enable esn and antireplay support [v2,30/31] common/cnxk: dump device basic info to file [v2,31/31] net/cnxk: dumps device private information

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Sept. 5, 2022, 1:32 p.m. UTC

  From: Harman Kalra <hkalra@marvell.com>

Adding support for 98xx A1 pass chip.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
 drivers/common/cnxk/roc_model.c |  1 +
 drivers/common/cnxk/roc_model.h | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index bdbd9a96b2..04338311ec 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -65,6 +65,7 @@  static const struct model_db {
 	{VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"},
 	{VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
 	{VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
+	{VENDOR_CAVIUM, PART_98xx, 0, 1, ROC_MODEL_CN98xx_A1, "cn98xx_a1"},
 	{VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
 	{VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
 	{VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index d231d44b60..57a8af06fc 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -21,6 +21,7 @@  struct roc_model {
 #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
 #define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
 #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
+#define ROC_MODEL_CN98xx_A1    BIT_ULL(17)
 #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
 #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
 #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
@@ -38,10 +39,11 @@  struct roc_model {
 } __plt_cache_aligned;
 
 #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
+#define ROC_MODEL_CN98xx_Ax (ROC_MODEL_CN98xx_A0 | ROC_MODEL_CN98xx_A1)
 #define ROC_MODEL_CN9K                                                         \
 	(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
 	 ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
-	 ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
+	 ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_Ax | \
 	 ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
 #define ROC_MODEL_CNF9K                                                        \
 	(ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
@@ -110,10 +112,22 @@  roc_model_is_cn10k(void)
 
 static inline uint64_t
 roc_model_is_cn98xx(void)
+{
+	return (roc_model->flag & ROC_MODEL_CN98xx_Ax);
+}
+
+static inline uint64_t
+roc_model_is_cn98xx_a0(void)
 {
 	return (roc_model->flag & ROC_MODEL_CN98xx_A0);
 }
 
+static inline uint64_t
+roc_model_is_cn98xx_a1(void)
+{
+	return (roc_model->flag & ROC_MODEL_CN98xx_A1);
+}
+
 static inline uint64_t
 roc_model_is_cn96_a0(void)
 {