From patchwork Mon Sep 5 10:58:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 115903 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 508DEA054F; Mon, 5 Sep 2022 12:59:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3FFE642B88; Mon, 5 Sep 2022 12:59:04 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 79CDC42B98 for ; Mon, 5 Sep 2022 12:59:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662375542; x=1693911542; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=164M8h1yBnwAgW8dO99cfy2J/FQ1wMgfzAW9YpCgjEs=; b=DUa4NZBgGQk62zn69MRA0awqZZc8VUseGM5K1DCXEFV/m7grTJR0zkbn su4rhCaLemn/QdTHaF2lZDhUGfmlYnps9LsrNTXf0f0w5YWk3dtNjYubj 092PjBIFAZMW+7H58Dsyr/BVjZ2HD0d/mJyqSm60uDn0veCJqtkNA9jEO yYkfY0UCQIjNwYT4mNPrNWj0aPlhwnLY7rSqIp+DQmrX6jrBFXtI4EAWN inbJ23kTZe0NhfsteehOwIr4zw3CgQIfJrAlpoMKIeDIpa8QCUPrtvMRl Z1puiWJtACHtKhQT97z3YpmRz3jLHTYP8y2zbaxYUpOefyZ67xudYryJc g==; X-IronPort-AV: E=McAfee;i="6500,9779,10460"; a="297676352" X-IronPort-AV: E=Sophos;i="5.93,291,1654585200"; d="scan'208";a="297676352" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2022 03:59:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,291,1654585200"; d="scan'208";a="682023948" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.118.246]) by fmsmga004.fm.intel.com with ESMTP; 05 Sep 2022 03:59:00 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Cc: dev@dpdk.org, xiao.w.wang@intel.com, junfeng.guo@intel.com Subject: [PATCH v2 12/14] net/idpf: add support for write back based on ITR expire Date: Mon, 5 Sep 2022 18:58:26 +0800 Message-Id: <20220905105828.3190335-13-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905105828.3190335-1-junfeng.guo@intel.com> References: <20220803113104.1184059-1-junfeng.guo@intel.com> <20220905105828.3190335-1-junfeng.guo@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Force write-backs by setting WB_ON_ITR bit in DYN_CTL register, so that the packets can be received once at a time. Signed-off-by: Beilei Xing Signed-off-by: Junfeng Guo --- drivers/net/idpf/idpf_ethdev.c | 116 +++++++++++++++++++++++++++++++++ drivers/net/idpf/idpf_ethdev.h | 3 + drivers/net/idpf/idpf_vchnl.c | 108 ++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c index 9fee7a783f..b3ca4e3326 100644 --- a/drivers/net/idpf/idpf_ethdev.c +++ b/drivers/net/idpf/idpf_ethdev.c @@ -520,6 +520,87 @@ idpf_dev_configure(struct rte_eth_dev *dev) return ret; } +static int +idpf_config_rx_queues_irqs(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + struct virtchnl2_queue_vector *qv_map; + struct iecm_hw *hw = &adapter->hw; + uint32_t dynctl_reg_start; + uint32_t itrn_reg_start; + uint32_t dynctl_val, itrn_val; + uint16_t i; + + qv_map = rte_zmalloc("qv_map", + dev->data->nb_rx_queues * + sizeof(struct virtchnl2_queue_vector), 0); + if (!qv_map) { + PMD_DRV_LOG(ERR, "Failed to allocate %d queue-vector map", + dev->data->nb_rx_queues); + goto qv_map_alloc_err; + } + + /* Rx interrupt disabled, Map interrupt only for writeback */ + + /* The capability flags adapter->caps->other_caps here should be + * compared with bit VIRTCHNL2_CAP_WB_ON_ITR. The if condition should + * be updated when the FW can return correct flag bits. + */ + if (adapter->caps->other_caps) { + dynctl_reg_start = vport->recv_vectors->vchunks.vchunks->dynctl_reg_start; + itrn_reg_start = vport->recv_vectors->vchunks.vchunks->itrn_reg_start; + dynctl_val = IECM_READ_REG(hw, dynctl_reg_start); + PMD_DRV_LOG(DEBUG, "Value of dynctl_reg_start is 0x%x", dynctl_val); + itrn_val = IECM_READ_REG(hw, itrn_reg_start); + PMD_DRV_LOG(DEBUG, "Value of itrn_reg_start is 0x%x", itrn_val); + /* Force write-backs by setting WB_ON_ITR bit in DYN_CTL + * register. WB_ON_ITR and INTENA are mutually exclusive + * bits. Setting WB_ON_ITR bits means TX and RX Descs + * are writen back based on ITR expiration irrespective + * of INTENA setting. + */ + /* TBD: need to tune INTERVAL value for better performance. */ + if (itrn_val) + IECM_WRITE_REG(hw, + dynctl_reg_start, + VIRTCHNL2_ITR_IDX_0 << + PF_GLINT_DYN_CTL_ITR_INDX_S | + PF_GLINT_DYN_CTL_WB_ON_ITR_M | + itrn_val << + PF_GLINT_DYN_CTL_INTERVAL_S); + else + IECM_WRITE_REG(hw, + dynctl_reg_start, + VIRTCHNL2_ITR_IDX_0 << + PF_GLINT_DYN_CTL_ITR_INDX_S | + PF_GLINT_DYN_CTL_WB_ON_ITR_M | + IDPF_DFLT_INTERVAL << + PF_GLINT_DYN_CTL_INTERVAL_S); + } + for (i = 0; i < dev->data->nb_rx_queues; i++) { + /* map all queues to the same vector */ + qv_map[i].queue_id = vport->chunks_info.rx_start_qid + i; + qv_map[i].vector_id = + vport->recv_vectors->vchunks.vchunks->start_vector_id; + } + vport->qv_map = qv_map; + + if (idpf_config_irq_map_unmap(vport, true)) { + PMD_DRV_LOG(ERR, "config interrupt mapping failed"); + goto config_irq_map_err; + } + + return 0; + +config_irq_map_err: + rte_free(vport->qv_map); + vport->qv_map = NULL; + +qv_map_alloc_err: + return -1; +} + static int idpf_start_queues(struct rte_eth_dev *dev) { @@ -557,6 +638,10 @@ static int idpf_dev_start(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + uint16_t num_allocated_vectors = + adapter->caps->num_allocated_vectors; + uint16_t req_vecs_num; PMD_INIT_FUNC_TRACE(); @@ -569,6 +654,23 @@ idpf_dev_start(struct rte_eth_dev *dev) vport->max_pkt_len = dev->data->mtu + IDPF_ETH_OVERHEAD; + req_vecs_num = IDPF_DFLT_Q_VEC_NUM; + if (req_vecs_num + adapter->used_vecs_num > num_allocated_vectors) { + PMD_DRV_LOG(ERR, "The accumulated request vectors' number should be less than %d", + num_allocated_vectors); + goto err_mtu; + } + if (idpf_alloc_vectors(vport, req_vecs_num)) { + PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); + goto err_mtu; + } + adapter->used_vecs_num += req_vecs_num; + + if (idpf_config_rx_queues_irqs(dev)) { + PMD_DRV_LOG(ERR, "Failed to configure irqs"); + goto err_mtu; + } + if (idpf_start_queues(dev)) { PMD_DRV_LOG(ERR, "Failed to start queues"); goto err_mtu; @@ -609,6 +711,12 @@ idpf_dev_stop(struct rte_eth_dev *dev) idpf_stop_queues(dev); + if (idpf_config_irq_map_unmap(vport, false)) + PMD_DRV_LOG(ERR, "config interrupt unmapping failed"); + + if (idpf_dealloc_vectors(vport)) + PMD_DRV_LOG(ERR, "deallocate interrupt vectors failed"); + vport->stopped = 1; dev->data->dev_started = 0; @@ -633,6 +741,12 @@ idpf_dev_close(struct rte_eth_dev *dev) rte_free(vport->rss_key); vport->rss_key = NULL; + rte_free(vport->recv_vectors); + vport->recv_vectors = NULL; + + rte_free(vport->qv_map); + vport->qv_map = NULL; + adapter->cur_vports &= ~BIT(vport->devarg_id); rte_free(vport); @@ -982,6 +1096,8 @@ idpf_adapter_init(struct rte_pci_device *pci_dev, struct idpf_adapter *adapter) adapter->cur_vport_nb = 0; adapter->next_vport_idx = 0; + adapter->used_vecs_num = 0; + return ret; err_vports: diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h index 2657b75c95..f96867f3d5 100644 --- a/drivers/net/idpf/idpf_ethdev.h +++ b/drivers/net/idpf/idpf_ethdev.h @@ -252,6 +252,9 @@ int idpf_ena_dis_queues(struct idpf_vport *vport, bool enable); int idpf_ena_dis_vport(struct idpf_vport *vport, bool enable); int idpf_query_stats(struct idpf_vport *vport, struct virtchnl2_vport_stats **pstats); +int idpf_config_irq_map_unmap(struct idpf_vport *vport, bool map); +int idpf_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors); +int idpf_dealloc_vectors(struct idpf_vport *vport); int idpf_query_ptype_info(struct idpf_adapter *adapter); int idpf_read_one_msg(struct idpf_adapter *adapter, uint32_t ops, uint16_t buf_len, uint8_t *buf); diff --git a/drivers/net/idpf/idpf_vchnl.c b/drivers/net/idpf/idpf_vchnl.c index 49572dc83c..97fcfb574b 100644 --- a/drivers/net/idpf/idpf_vchnl.c +++ b/drivers/net/idpf/idpf_vchnl.c @@ -1133,6 +1133,114 @@ idpf_config_txq(struct idpf_vport *vport, uint16_t txq_id) return err; } + +int +idpf_config_irq_map_unmap(struct idpf_vport *vport, bool map) +{ + struct idpf_adapter *adapter = vport->adapter; + struct virtchnl2_queue_vector_maps *map_info; + struct virtchnl2_queue_vector *vecmap; + uint16_t nb_rxq = vport->dev_data->nb_rx_queues; + struct idpf_cmd_info args; + int len, i, err = 0; + + len = sizeof(struct virtchnl2_queue_vector_maps) + + (nb_rxq - 1) * sizeof(struct virtchnl2_queue_vector); + + map_info = rte_zmalloc("map_info", len, 0); + if (!map_info) + return -ENOMEM; + + map_info->vport_id = vport->vport_id; + map_info->num_qv_maps = nb_rxq; + for (i = 0; i < nb_rxq; i++) { + vecmap = &map_info->qv_maps[i]; + vecmap->queue_id = vport->qv_map[i].queue_id; + vecmap->vector_id = vport->qv_map[i].vector_id; + vecmap->itr_idx = VIRTCHNL2_ITR_IDX_0; + vecmap->queue_type = VIRTCHNL2_QUEUE_TYPE_RX; + } + + args.ops = map ? VIRTCHNL2_OP_MAP_QUEUE_VECTOR : + VIRTCHNL2_OP_UNMAP_QUEUE_VECTOR; + args.in_args = (u8 *)map_info; + args.in_args_size = len; + args.out_buffer = adapter->mbx_resp; + args.out_size = IDPF_DFLT_MBX_BUF_SIZE; + err = idpf_execute_vc_cmd(adapter, &args); + if (err) + PMD_DRV_LOG(ERR, "Failed to execute command of VIRTCHNL2_OP_%s_QUEUE_VECTOR", + map ? "MAP" : "UNMAP"); + + rte_free(map_info); + return err; +} + +int +idpf_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors) +{ + struct idpf_adapter *adapter = vport->adapter; + struct virtchnl2_alloc_vectors *alloc_vec; + struct idpf_cmd_info args; + int err, len; + + len = sizeof(struct virtchnl2_alloc_vectors) + + (num_vectors - 1) * sizeof(struct virtchnl2_vector_chunk); + alloc_vec = rte_zmalloc("alloc_vec", len, 0); + if (!alloc_vec) + return -ENOMEM; + + alloc_vec->num_vectors = num_vectors; + + args.ops = VIRTCHNL2_OP_ALLOC_VECTORS; + args.in_args = (u8 *)alloc_vec; + args.in_args_size = sizeof(struct virtchnl2_alloc_vectors); + args.out_buffer = adapter->mbx_resp; + args.out_size = IDPF_DFLT_MBX_BUF_SIZE; + err = idpf_execute_vc_cmd(adapter, &args); + if (err) + PMD_DRV_LOG(ERR, "Failed to execute command VIRTCHNL2_OP_ALLOC_VECTORS"); + + if (!vport->recv_vectors) { + vport->recv_vectors = rte_zmalloc("recv_vectors", len, 0); + if (!vport->recv_vectors) { + rte_free(alloc_vec); + return -ENOMEM; + } + } + + rte_memcpy(vport->recv_vectors, args.out_buffer, len); + rte_free(alloc_vec); + return err; +} + +int +idpf_dealloc_vectors(struct idpf_vport *vport) +{ + struct idpf_adapter *adapter = vport->adapter; + struct virtchnl2_alloc_vectors *alloc_vec; + struct virtchnl2_vector_chunks *vcs; + struct idpf_cmd_info args; + int err, len; + + alloc_vec = vport->recv_vectors; + vcs = &alloc_vec->vchunks; + + len = sizeof(struct virtchnl2_vector_chunks) + + (vcs->num_vchunks - 1) * sizeof(struct virtchnl2_vector_chunk); + + args.ops = VIRTCHNL2_OP_DEALLOC_VECTORS; + args.in_args = (u8 *)vcs; + args.in_args_size = len; + args.out_buffer = adapter->mbx_resp; + args.out_size = IDPF_DFLT_MBX_BUF_SIZE; + err = idpf_execute_vc_cmd(adapter, &args); + if (err) + PMD_DRV_LOG(ERR, "Failed to execute command VIRTCHNL2_OP_DEALLOC_VECTORS"); + + return err; +} + static int idpf_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid, uint32_t type, bool on)