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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CY4PEPF0000B8ED.mail.protection.outlook.com (10.167.241.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5588.7 via Frontend Transport; Thu, 1 Sep 2022 08:17:22 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Thu, 1 Sep 2022 08:17:21 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 1 Sep 2022 01:17:20 -0700 From: Gerry Gribbon To: CC: , Ori Kam Subject: [PATCH] regexdev: add maximum number of mbuf segments field Date: Thu, 1 Sep 2022 08:16:54 +0000 Message-ID: <20220901081655.2434317-1-ggribbon@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd9e2713-940f-436d-c823-08da8bf26549 X-MS-TrafficTypeDiagnostic: SN7PR12MB7347:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2022 08:17:22.2777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd9e2713-940f-436d-c823-08da8bf26549 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7347 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allows application to query maximum number of mbuf segments that can be chained together. Signed-off-by: Gerry Gribbon Acked-by: Ori Kam --- drivers/regex/mlx5/mlx5_regex.h | 1 + drivers/regex/mlx5/mlx5_regex_fastpath.c | 43 ++++++++++++++++++++++++ drivers/regex/mlx5/mlx5_rxp.c | 1 + lib/regexdev/rte_regexdev.h | 2 ++ 4 files changed, 47 insertions(+) diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 89495301ac..98fe95b781 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -94,4 +94,5 @@ uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, struct rte_regex_ops **ops, uint16_t nb_ops); uint16_t mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, struct rte_regex_ops **ops, uint16_t nb_ops); +uint16_t mlx5_regexdev_max_segs_get(void); #endif /* MLX5_REGEX_H */ diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 9a2db7e43f..16f48627e5 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -41,6 +41,39 @@ /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */ #define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \ (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2)) +#ifdef RTE_LIBRTE_MLX5_DEBUG +#define MLX5_REGEX_DEBUG 0 +#endif +#ifdef HAVE_MLX5_UMR_IMKEY +static uint16_t max_nb_segs = MLX5_REGEX_MAX_KLM_NUM; +#else +static uint16_t max_nb_segs = 1; +#endif + +uint16_t +mlx5_regexdev_max_segs_get(void) +{ + return max_nb_segs; +} + +#ifdef MLX5_REGEX_DEBUG +static inline uint16_t +validate_ops(struct rte_regex_ops **ops, uint16_t nb_ops) +{ + uint16_t nb_left = nb_ops; + struct rte_mbuf *mbuf; + + while (nb_left--) { + mbuf = ops[nb_left]->mbuf; + if ((mbuf->pkt_len > MLX5_RXP_MAX_JOB_LENGTH) || + (mbuf->nb_segs > max_nb_segs)) { + DRV_LOG(ERR, "Failed to validate regex ops"); + return 1; + } + } + return 0; +} +#endif static inline uint32_t qp_size_get(struct mlx5_regex_hw_qp *qp) @@ -375,6 +408,11 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, struct mlx5_regex_hw_qp *qp_obj; size_t hw_qpid, nb_left = nb_ops, nb_desc; +#ifdef MLX5_REGEX_DEBUG + if (validate_ops(ops, nb_ops)) + return 0; +#endif + while ((hw_qpid = ffs(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; @@ -409,6 +447,11 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, struct mlx5_regex_hw_qp *qp_obj; size_t hw_qpid, job_id, i = 0; +#ifdef MLX5_REGEX_DEBUG + if (validate_ops(ops, nb_ops)) + return 0; +#endif + while ((hw_qpid = ffs(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index ed3af15e40..35a4cfb7ac 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -45,6 +45,7 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused, RTE_REGEXDEV_CAPA_QUEUE_PAIR_OOS_F; info->rule_flags = 0; info->max_queue_pairs = UINT16_MAX; + info->max_num_mbuf_segs = mlx5_regexdev_max_segs_get(); return 0; } diff --git a/lib/regexdev/rte_regexdev.h b/lib/regexdev/rte_regexdev.h index 3bce8090f6..131d44f474 100644 --- a/lib/regexdev/rte_regexdev.h +++ b/lib/regexdev/rte_regexdev.h @@ -612,6 +612,8 @@ struct rte_regexdev_info { /**< Maximum payload size for a pattern match request or scan. * @see RTE_REGEXDEV_CFG_CROSS_BUFFER_SCAN_F */ + uint16_t max_num_mbuf_segs; + /**< Maximum number of mbuf segments that can be chained together. */ uint32_t max_rules_per_group; /**< Maximum rules supported per group by this device. */ uint16_t max_groups;