From patchwork Sat Aug 20 02:31:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115264 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D20EFA034C; Fri, 19 Aug 2022 20:36:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23DC84282D; Fri, 19 Aug 2022 20:36:20 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id A02AA40E2D for ; Fri, 19 Aug 2022 20:36:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934174; x=1692470174; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFJIG3xNNzqYduatFXqHOsemCIW+RzkoeSFVTcmhjUM=; b=X3vJQauyeuvT5XKnfq6VNacKUg6kgyvJgu9/+r+EQdVdjn87oN8zLOwi J5Y7kWFkkiwsXR/P0XGm+7bVfC062xQ999Ufv313IyjB7qmL+PQIpVOCz zO9XrNVbgYsFGXO0HO9HpxYI9I2KedODomRq+GTe4uhBBczSExvlAqNXN D72dzM1GbrvGRCMazvFytL11+965lMJH6SwfLeGKDOZi0iP7ukR2gogcL onU9fbmyAOakmtXybnsK9u2mnJR9Q78kzqZYUqoOwhrYLq4oaueLRsSBL z0BlW7kqwPKBKNkpyfcN6lNwDB7AKUxt7W0ebbCRb/a00hsJ0lTrKymne w==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107223" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107223" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296253" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:13 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v2 06/37] baseband/acc100: add default e value for FCW Date: Fri, 19 Aug 2022 19:31:26 -0700 Message-Id: <20220820023157.189047-7-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor frame control word LDPC encoder fill function to take a default e value as a parameter. No functional impact. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 586d06d1b3..cc7d146e74 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1268,7 +1268,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) /* Fill in a frame control word for LDPC encoding. */ static inline void acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, - struct acc100_fcw_le *fcw, int num_cb) + struct acc100_fcw_le *fcw, int num_cb, uint32_t default_e) { fcw->qm = op->ldpc_enc.q_m; fcw->nfiller = op->ldpc_enc.n_filler; @@ -1277,7 +1277,7 @@ acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, fcw->ncb = op->ldpc_enc.n_cb; fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_enc.basegraph, op->ldpc_enc.rv_index); - fcw->rm_e = op->ldpc_enc.cb_params.e; + fcw->rm_e = (default_e == 0) ? op->ldpc_enc.cb_params.e : default_e; fcw->crc_select = check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH); fcw->bypass_intlv = check_bit(op->ldpc_enc.op_flags, @@ -2525,7 +2525,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num); + acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); /** This could be done at polling */ acc100_header_init(&desc->req); @@ -2587,7 +2587,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(op, &desc->req.fcw_le, 1); + acc100_fcw_le_fill(op, &desc->req.fcw_le, 1, 0); input = op->ldpc_enc.input.data; output_head = output = op->ldpc_enc.output.data;