diff mbox series

[v2,22/37] baseband/acc100: enforce additional check on FCW

Message ID 20220820023157.189047-23-hernan.vargas@intel.com (mailing list archive)
State Superseded, archived
Delegated to: akhil goyal
Headers show
Series baseband/acc100: changes for 22.11 | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Hernan Vargas Aug. 20, 2022, 2:31 a.m. UTC
Enforce additional check on Frame Control Word validity and add stronger
alignment for decompression mode.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
 drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 3 deletions(-)

Comments

Maxime Coquelin Sept. 15, 2022, 10:12 a.m. UTC | #1
On 8/20/22 04:31, Hernan Vargas wrote:
> Enforce additional check on Frame Control Word validity and add stronger
> alignment for decompression mode.

As on previous patches, it is a fix and so should be marked
appropriately and moved at the beginning of the series.

> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
>   drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++--
>   1 file changed, 37 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index ea850e2d7f..d67495ac52 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1508,6 +1508,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
>   		fcw->hcin_offset = 0;
>   		fcw->hcin_size1 = 0;
>   	}
> +	/* Enforce additional check on FCW validity */
> +	uint32_t max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, 64);

Don't mix declaration and code.

> +	if ((fcw->hcin_size0 > max_hc_in) ||
> +			(fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) ||
> +			((fcw->hcin_size0 > fcw->hcin_offset) &&
> +			(fcw->hcin_size1 != 0))) {
> +		rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d",
> +				fcw->hcin_size0, fcw->hcin_size1,
> +				fcw->hcin_offset,
> +				fcw->ncb, fcw->nfiller);
> +		/* Disable HARQ input in that case to carry forward */
> +		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> +		fcw->hcin_en = 0;
> +	}
>   
>   	fcw->itmax = op->ldpc_dec.iter_max;
>   	fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> @@ -1536,10 +1550,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
>   		k0_p = (fcw->k0 > parity_offset) ?
>   				fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
>   		ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> -		l = k0_p + fcw->rm_e;
> +		l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
>   		harq_out_length = (uint16_t) fcw->hcin_size0;
> -		harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p);
> -		harq_out_length = (harq_out_length + 0x3F) & 0xFFC0;
> +		harq_out_length = RTE_MAX(harq_out_length, l);
> +		/* Stronger alignment when in compression mode */
> +		if (fcw->hcout_comp_mode > 0)
> +			harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 256);

A define would make sense instead of raw value

> +		/* Cannot exceed the pruned Ncb circular buffer */
> +		harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> +		/* Alignment on next 64B */
> +		harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> +		/* Stronger alignment when in compression mode enforced again */
> +		if (fcw->hcout_comp_mode > 0)
> +			harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, 256);
>   		if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) &&
>   				harq_prun) {
>   			fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
> @@ -1550,6 +1573,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
>   			fcw->hcout_size1 = 0;
>   			fcw->hcout_offset = 0;
>   		}
> +		if (fcw->hcout_size0 == 0) {
> +			rte_bbdev_log(ERR, " Invalid FCW : HCout %d",
> +				fcw->hcout_size0);
> +			op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
> +			fcw->hcout_en = 0;
> +		}
> +
>   		harq_layout[harq_index].offset = fcw->hcout_offset;
>   		harq_layout[harq_index].size0 = fcw->hcout_size0;
>   	} else {
> @@ -1591,6 +1621,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
>   		/* Disable HARQ input in that case to carry forward */
>   		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
>   	}
> +	if (unlikely(fcw->rm_e == 0)) {
> +		rte_bbdev_log(WARNING, "Null E input provided");
> +		fcw->rm_e = 2;
> +	}
>   
>   	fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
>   			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
diff mbox series

Patch

diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index ea850e2d7f..d67495ac52 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1508,6 +1508,20 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
 		fcw->hcin_offset = 0;
 		fcw->hcin_size1 = 0;
 	}
+	/* Enforce additional check on FCW validity */
+	uint32_t max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, 64);
+	if ((fcw->hcin_size0 > max_hc_in) ||
+			(fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) ||
+			((fcw->hcin_size0 > fcw->hcin_offset) &&
+			(fcw->hcin_size1 != 0))) {
+		rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d",
+				fcw->hcin_size0, fcw->hcin_size1,
+				fcw->hcin_offset,
+				fcw->ncb, fcw->nfiller);
+		/* Disable HARQ input in that case to carry forward */
+		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+		fcw->hcin_en = 0;
+	}
 
 	fcw->itmax = op->ldpc_dec.iter_max;
 	fcw->itstop = check_bit(op->ldpc_dec.op_flags,
@@ -1536,10 +1550,19 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
 		k0_p = (fcw->k0 > parity_offset) ?
 				fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
 		ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
-		l = k0_p + fcw->rm_e;
+		l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
 		harq_out_length = (uint16_t) fcw->hcin_size0;
-		harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p);
-		harq_out_length = (harq_out_length + 0x3F) & 0xFFC0;
+		harq_out_length = RTE_MAX(harq_out_length, l);
+		/* Stronger alignment when in compression mode */
+		if (fcw->hcout_comp_mode > 0)
+			harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 256);
+		/* Cannot exceed the pruned Ncb circular buffer */
+		harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+		/* Alignment on next 64B */
+		harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+		/* Stronger alignment when in compression mode enforced again */
+		if (fcw->hcout_comp_mode > 0)
+			harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, 256);
 		if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) &&
 				harq_prun) {
 			fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
@@ -1550,6 +1573,13 @@  acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
 			fcw->hcout_size1 = 0;
 			fcw->hcout_offset = 0;
 		}
+		if (fcw->hcout_size0 == 0) {
+			rte_bbdev_log(ERR, " Invalid FCW : HCout %d",
+				fcw->hcout_size0);
+			op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+			fcw->hcout_en = 0;
+		}
+
 		harq_layout[harq_index].offset = fcw->hcout_offset;
 		harq_layout[harq_index].size0 = fcw->hcout_size0;
 	} else {
@@ -1591,6 +1621,10 @@  acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
 		/* Disable HARQ input in that case to carry forward */
 		op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
 	}
+	if (unlikely(fcw->rm_e == 0)) {
+		rte_bbdev_log(WARNING, "Null E input provided");
+		fcw->rm_e = 2;
+	}
 
 	fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
 			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);