From patchwork Sat Aug 20 02:31:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vargas, Hernan" X-Patchwork-Id: 115271 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6DEFA034C; Fri, 19 Aug 2022 20:37:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4707242B94; Fri, 19 Aug 2022 20:36:26 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 6CFCA427F9 for ; Fri, 19 Aug 2022 20:36:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934178; x=1692470178; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yfllDSbsqF7rnFwYtJbrmCj549bVbBDsWZAyaKkd//A=; b=Eb6+O3BKa4CFzJgzr+PJWjAx4IlaGfXXm2P8R+nDgpKHQHrrqElQVJGS MMOXIbsWIULUBOmDKYAjdAd+f9EXhAhYxq3I8gxb9F0zNhejYLyBc9OuJ htzTEJi0Jg3aKU4dmP+T0UL/cniirgQe81lN+iUVIbNnxT44CeBUfExBo RbexcxXhyk56rItPUrPvy16S81S+7G+8fCBx1K16v2sH8e7CvD53iFhwn Jjae90r+BLMV7A8FaESJNsnIHk6XkQMKghnQGmoU0hzcr7QWhVeHl2K34 sFcRBM0n3LnLkig8DEr4VJJQmVft/881jpIn4rN7+SRhrjtKLtjnca2cu w==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107255" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107255" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296285" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:17 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning Date: Fri, 19 Aug 2022 19:31:33 -0700 Message-Id: <20220820023157.189047-14-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add flag ACC101_HARQ_PRUNING_OPTIMIZATION to limit cases when HARQ pruning is valid. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 52 +++++++++++++++++++----- 1 file changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 81bae4d695..e47f7d68c2 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1370,17 +1370,23 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ +#ifdef ACC100_HARQ_PRUNING_OPTIMIZATION harq_prun = ((op->ldpc_dec.harq_combined_output.offset % - ACC100_HARQ_OFFSET) == 0) && - (op->ldpc_dec.harq_combined_output.offset <= UINT16_MAX - * ACC100_HARQ_OFFSET); + ACC100_HARQ_OFFSET) == 0); +#endif #endif if (fcw->hcin_en > 0) { harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 256); + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; @@ -1455,6 +1461,7 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; uint32_t harq_index; uint32_t l; + bool harq_prun = false; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1500,6 +1507,13 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); + #ifdef ACC100_EXT_MEM + /* Limit cases when HARQ pruning is valid */ +#ifdef ACC101_HARQ_PRUNING_OPTIMIZATION + harq_prun = ((op->ldpc_dec.harq_combined_output.offset % + ACC101_HARQ_OFFSET) == 0); +#endif +#endif if (fcw->hcin_en > 0) { harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) @@ -1508,9 +1522,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, - op->ldpc_dec.n_filler); /* Alignment on next 64B - Already enforced from HC output */ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); - fcw->hcin_size0 = harq_in_length; - fcw->hcin_offset = 0; - fcw->hcin_size1 = 0; + if ((harq_layout[harq_index].offset > 0) && harq_prun) { + rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); + fcw->hcin_size0 = harq_layout[harq_index].size0; + fcw->hcin_offset = harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - + harq_layout[harq_index].offset; + } else { + fcw->hcin_size0 = harq_in_length; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } } else { fcw->hcin_size0 = 0; fcw->hcin_offset = 0; @@ -1551,9 +1573,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, harq_out_length = RTE_MIN(harq_out_length, ncb_p); /* Alignment on next 64B */ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); - fcw->hcout_size0 = harq_out_length; - fcw->hcout_size1 = 0; - fcw->hcout_offset = 0; + if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && + harq_prun) { + fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; + fcw->hcout_offset = k0_p & 0xFFC0; + fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; + } else { + fcw->hcout_size0 = harq_out_length; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else {