From patchwork Thu Aug 11 09:14:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 114834 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8728A0548; Thu, 11 Aug 2022 11:14:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 682EB40DDA; Thu, 11 Aug 2022 11:14:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7F793400D6 for ; Thu, 11 Aug 2022 11:14:53 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27B7t49A025380 for ; Thu, 11 Aug 2022 02:14:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=EHfoSJs3IVj+2RK4rLrZZWtC2BDJMCynu4id7jqlsbI=; b=aO8la30GNgFihuB2NqT5Z4sbWV81JUOulHrzqPTJSj6bxSldl7mwJ59wOw24QutpAYBc R/QbT0ZzGQ8CwanVjCwSIHZP8wVEcaaDLr83ZvMMTTacjg0cRji76gcQcTG7YaGrXZFS 2QKlaoY+7TPuuT02i380MgVD5C7dXif7OgKhjbFxy+/E/PG9W/LmpuHw1NuTUHtAuy/E +DoGhzPAMGijSc4+lPwRPVroi2C+ECjwCrXOh7qnP6BFBQRip+LR2ckoxY7SAVV9PfFt OQwJzxDxk8ujkuljVUxlJaHbynQNiLxv0sC01VGnjWr4eMO3ybn/55we7Qzxs8QPx+4A LA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3hvwsp88sc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 11 Aug 2022 02:14:52 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 11 Aug 2022 02:14:46 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 11 Aug 2022 02:14:46 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id E86B63F7081; Thu, 11 Aug 2022 02:14:44 -0700 (PDT) From: Srujana Challa To: , , , CC: , Subject: [PATCH] common/cnxk: add CPT LF reset sequence Date: Thu, 11 Aug 2022 14:44:43 +0530 Message-ID: <20220811091443.3071511-1-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: hH2XEqqJDnjhUbfAmDXfUrHYJ3ETV6WO X-Proofpoint-GUID: hH2XEqqJDnjhUbfAmDXfUrHYJ3ETV6WO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-11_05,2022-08-10_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds code to reset CPT LF as part of cpt_lf_fini. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 82 ++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_mbox.h | 6 +++ 2 files changed, 88 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index f1be6a3401..a48696f379 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -712,6 +712,87 @@ roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr) return 0; } +static int +cpt_lf_reset(struct roc_cpt_lf *lf) +{ + struct cpt_lf_rst_req *req; + struct dev *dev = lf->dev; + + req = mbox_alloc_msg_cpt_lf_reset(dev->mbox); + if (req == NULL) + return -EIO; + + req->slot = lf->lf_id; + + return mbox_process(dev->mbox); +} + +static void +cpt_9k_lf_rst_lmtst(struct roc_cpt_lf *lf, uint8_t egrp) +{ + struct cpt_inst_s inst; + uint64_t lmt_status; + + memset(&inst, 0, sizeof(struct cpt_inst_s)); + inst.w7.s.egrp = egrp; + + plt_io_wmb(); + + do { + /* Copy CPT command to LMTLINE */ + roc_lmt_mov64((void *)lf->lmt_base, &inst); + lmt_status = roc_lmt_submit_ldeor(lf->io_addr); + } while (lmt_status == 0); +} + +static void +cpt_10k_lf_rst_lmtst(struct roc_cpt_lf *lf, uint8_t egrp) +{ + uint64_t lmt_base, lmt_arg, io_addr; + struct cpt_inst_s *inst; + uint16_t lmt_id; + + lmt_base = lf->lmt_base; + io_addr = lf->io_addr; + + io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4; + ROC_LMT_BASE_ID_GET(lmt_base, lmt_id); + + inst = (struct cpt_inst_s *)lmt_base; + memset(inst, 0, sizeof(struct cpt_inst_s)); + inst->w7.s.egrp = egrp; + lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id; + roc_lmt_submit_steorl(lmt_arg, io_addr); +} + +static void +roc_cpt_iq_reset(struct roc_cpt_lf *lf) +{ + union cpt_lf_inprog lf_inprog = {.u = 0x0}; + union cpt_lf_ctl lf_ctl = {.u = 0x0}; + + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + if (((lf_inprog.s.gwb_cnt & 0x1) == 0x1) && + (lf_inprog.s.grb_partial == 0x0)) { + lf_inprog.s.grp_drp = 1; + plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + + lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL); + lf_ctl.s.ena = 1; + plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); + + if (roc_model_is_cn10k()) + cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); + else + cpt_9k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); + + plt_read64(lf->rbase + CPT_LF_INPROG); + plt_delay_us(2); + } + if (cpt_lf_reset(lf)) + plt_err("Invalid CPT LF to reset"); +} + void cpt_lf_fini(struct roc_cpt_lf *lf) { @@ -720,6 +801,7 @@ cpt_lf_fini(struct roc_cpt_lf *lf) /* Disable IQ */ roc_cpt_iq_disable(lf); + roc_cpt_iq_reset(lf); /* Free memory */ plt_free(lf->iq_vaddr); diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 965c704322..b6dee69ac8 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -151,6 +151,7 @@ struct mbox_msghdr { M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ msg_rsp) \ M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ + M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \ cpt_rx_inline_lf_cfg_msg, msg_rsp) \ M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \ @@ -1511,6 +1512,11 @@ struct cpt_eng_grp_rsp { uint8_t __io eng_grp_num; }; +struct cpt_lf_rst_req { + struct mbox_msghdr hdr; + uint32_t __io slot; +}; + /* REE mailbox error codes * Range 1001 - 1100. */