From patchwork Tue Aug 9 18:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114785 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 756E3A04FD; Tue, 9 Aug 2022 20:52:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6198C42BD6; Tue, 9 Aug 2022 20:52:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 174EF42BDA for ; Tue, 9 Aug 2022 20:52:07 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279CnFCa017235; Tue, 9 Aug 2022 11:50:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=vBTselbWV2x7VrszG2EyGf2sDidPVkXpetJYb9FWaPA=; b=HtJqG6zSgXHFE++J9U80GxHbGUq6mcqBfbrllci3V2Gq56SE/y0tlNixriLODP6tFRpf c1PML0FC75iKmyyoa7CopqwoLucI+NXrNAp/ySgyGfz3RYES4KZtkr3z+KSyBvVXFqAi zJoLsAQ661eLdUqhH30WhbDx6i1u1g1hWxWxz245SbK0sTbzZtIZG7s76HluLAjCo27w SdsXdxLhBX6CPnKN3oOlK44o4lWJPtTxy4LbYYTYs8RN6oLyBjosNuZpkDlNKv18qtKn soY2KKxOD+yWt2McXkCMpENLYrYdOMGftmB4ZnZlUgWQPkLI2OjwUOFLYLOfnoIKoV4k EQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hudy6ujqv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 09 Aug 2022 11:50:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:49:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:49:59 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3A40E3F7086; Tue, 9 Aug 2022 11:49:56 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 06/23] common/cnxk: delay inline device RQ enable to dev start Date: Wed, 10 Aug 2022 00:18:50 +0530 Message-ID: <20220809184908.24030-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -spcDmKxLEXNLLRIGNhi0dBAj2fm5rEn X-Proofpoint-ORIG-GUID: -spcDmKxLEXNLLRIGNhi0dBAj2fm5rEn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Similar to other RQ's, delay inline device rq until dev is started to avoid traffic reception when device is stopped. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_idev.h | 2 -- drivers/common/cnxk/roc_nix_inl.c | 34 +++++++++++++++++++++++++++++++--- drivers/common/cnxk/roc_nix_inl.h | 5 ++++- drivers/common/cnxk/version.map | 7 ++++--- drivers/net/cnxk/cnxk_ethdev.c | 14 +++++++++++++- 5 files changed, 52 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 7e0beed..16793c2 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -17,6 +17,4 @@ void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt); struct roc_nix *__roc_api roc_idev_npa_nix_get(void); -uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix); - #endif /* _ROC_IDEV_H_ */ diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 603551b..c621867 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -245,6 +245,9 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags) struct roc_cpt *roc_cpt; struct roc_cpt_rxc_time_cfg cfg; + if (!idev) + return -EFAULT; + PLT_SET_USED(max_frags); if (idev == NULL) return -ENOTSUP; @@ -587,7 +590,7 @@ roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix) } int -roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) +roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) { struct idev_cfg *idev = idev_get_cfg(); int port_id = rq->roc_nix->port_id; @@ -688,9 +691,9 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) /* Prepare and send RQ init mbox */ if (roc_model_is_cn9k()) - rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true); + rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, enable); else - rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true); + rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, enable); if (rc) { plt_err("Failed to prepare aq_enq msg, rc=%d", rc); return rc; @@ -755,6 +758,31 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq) return rc; } +int +roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct roc_nix_rq *inl_rq = roc_nix_inl_dev_rq(roc_nix); + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev; + int rc; + + if (!idev) + return -EFAULT; + + if (nix->inb_inl_dev) { + if (!inl_rq || !idev->nix_inl_dev) + return -EFAULT; + + inl_dev = idev->nix_inl_dev; + + rc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable); + if (rc) + return rc; + } + return 0; +} + void roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index c7b1817..702ec01 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -165,7 +165,7 @@ uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inl_dev_sa, uint32_t spi); void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev); -int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq); +int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool ena); int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq); bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix); struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix); @@ -175,6 +175,7 @@ int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags); int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); +int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); @@ -189,6 +190,8 @@ int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args); int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll); +uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix); + /* NIX Inline/Outbound API */ enum roc_nix_inl_sa_sync_op { ROC_NIX_INL_SA_OP_FLUSH, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a2d99e1..6d43e37 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -90,7 +90,6 @@ INTERNAL { roc_hash_sha512_gen; roc_idev_cpt_get; roc_idev_cpt_set; - roc_nix_inl_outb_ring_base_get; roc_idev_lmt_base_addr_get; roc_idev_npa_maxpools_get; roc_idev_npa_maxpools_set; @@ -137,11 +136,13 @@ INTERNAL { roc_nix_get_vwqe_interval; roc_nix_inl_cb_register; roc_nix_inl_cb_unregister; + roc_nix_inl_ctx_write; roc_nix_inl_dev_dump; roc_nix_inl_dev_fini; roc_nix_inl_dev_init; roc_nix_inl_dev_is_probed; roc_nix_inl_dev_lock; + roc_nix_inl_dev_pffunc_get; roc_nix_inl_dev_rq; roc_nix_inl_dev_rq_get; roc_nix_inl_dev_rq_put; @@ -163,11 +164,11 @@ INTERNAL { roc_nix_inl_outb_sa_base_get; roc_nix_inl_outb_sso_pffunc_get; roc_nix_inl_outb_is_enabled; + roc_nix_inl_outb_ring_base_get; roc_nix_inl_outb_soft_exp_poll_switch; + roc_nix_inl_rq_ena_dis; roc_nix_inl_sa_sync; roc_nix_inl_ts_pkind_set; - roc_nix_inl_ctx_write; - roc_nix_inl_dev_pffunc_get; roc_nix_inl_outb_cpt_lfs_dump; roc_nix_cpt_ctx_cache_sync; roc_nix_is_lbk; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index df20f27..b3af2f8 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -660,7 +660,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28); /* Setup rq reference for inline dev if present */ - rc = roc_nix_inl_dev_rq_get(rq); + rc = roc_nix_inl_dev_rq_get(rq, !!eth_dev->data->dev_started); if (rc) goto free_mem; } @@ -1482,6 +1482,10 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, false); + /* Stop inline device RQ first */ + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) + roc_nix_inl_rq_ena_dis(&dev->nix, false); + /* Stop rx queues and free up pkts pending */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rc = dev_ops->rx_queue_stop(eth_dev, i); @@ -1527,6 +1531,14 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) return rc; } + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { + rc = roc_nix_inl_rq_ena_dis(&dev->nix, true); + if (rc) { + plt_err("Failed to enable Inline device RQ, rc=%d", rc); + return rc; + } + } + /* Start tx queues */ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { rc = cnxk_nix_tx_queue_start(eth_dev, i);