From patchwork Tue Aug 9 18:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114769 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4819CA04FD; Tue, 9 Aug 2022 20:50:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0E3C742BE2; Tue, 9 Aug 2022 20:50:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DE65142BCD for ; Tue, 9 Aug 2022 20:49:58 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D67Gl016173 for ; Tue, 9 Aug 2022 11:49:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bNVHLAPU6Gu4P0tYUCzN7VHPFqganzHREw7Z7cBSdDA=; b=RTtswHLjIiU1gr5U3Hgu/CbHjPtfwBDim59UJQm4VxntXOHjYzVjjtsrOn5nYPzTzeze Myhln5FwRdflHQAKy1tj92MzwqVlVBSzKjPglgub0ZMm4aZRY71QXR/Ukh2IXCyK/GSC Mjbr7VZtv3jQ+LK/I+sWEtPDHxML3Pefi5T9IoKSx7aReW5MAYjvMMPIZJGMXBa2Rfoa 88lplNhXN/9UG2ZAGSsjS96d81DMGY5gplWk5vYyfFbXbMx443y1+vvm7VT8GtDmSmKz +8s8YGRWxSf9AzuSbOqM/ORn8v03YS+HGH6tHBNypwNM3B4dJhxu29UaC3qq9z7SJm9j HA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukqn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Aug 2022 11:49:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:49:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:49:56 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A04433F7085; Tue, 9 Aug 2022 11:49:54 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0 Date: Wed, 10 Aug 2022 00:18:49 +0530 Message-ID: <20220809184908.24030-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: HY4KHJ-8jIzCbpNc1pjLp-2p2Z51QywO X-Proofpoint-GUID: HY4KHJ-8jIzCbpNc1pjLp-2p2Z51QywO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit meta aura workaround to CN10K A0. Also other NIX and Inline related Erratas applicable for CN10K A1. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_errata.h | 7 +++++++ drivers/common/cnxk/roc_nix_inl.c | 10 ++++++---- drivers/net/cnxk/cnxk_ethdev.c | 3 ++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index f048297..8dc372f 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -81,6 +81,13 @@ roc_errata_nix_has_perf_issue_on_stats_update(void) static inline bool roc_errata_cpt_hang_on_x2p_bp(void) { + return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1(); +} + +/* IPBUNIXRX-40400 */ +static inline bool +roc_errata_nix_no_meta_aura(void) +{ return roc_model_is_cn10ka_a0(); } diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 7da8938..603551b 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -627,18 +627,18 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) inl_rq->first_skip = rq->first_skip; inl_rq->later_skip = rq->later_skip; inl_rq->lpb_size = rq->lpb_size; - inl_rq->lpb_drop_ena = true; inl_rq->spb_ena = rq->spb_ena; inl_rq->spb_aura_handle = rq->spb_aura_handle; inl_rq->spb_size = rq->spb_size; - inl_rq->spb_drop_ena = !!rq->spb_ena; - if (!roc_model_is_cn9k()) { + if (roc_errata_nix_no_meta_aura()) { uint64_t aura_limit = roc_npa_aura_op_limit_get(inl_rq->aura_handle); uint64_t aura_shift = plt_log2_u32(aura_limit); uint64_t aura_drop, drop_pc; + inl_rq->lpb_drop_ena = true; + if (aura_shift < 8) aura_shift = 0; else @@ -653,12 +653,14 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true); } - if (inl_rq->spb_ena) { + if (roc_errata_nix_no_meta_aura() && inl_rq->spb_ena) { uint64_t aura_limit = roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle); uint64_t aura_shift = plt_log2_u32(aura_limit); uint64_t aura_drop, drop_pc; + inl_rq->spb_drop_ena = true; + if (aura_shift < 8) aura_shift = 0; else diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 2418290..df20f27 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -617,7 +617,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rq->first_skip = first_skip; rq->later_skip = sizeof(struct rte_mbuf); rq->lpb_size = mp->elt_size; - rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); + if (roc_errata_nix_no_meta_aura()) + rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); /* Enable Inline IPSec on RQ, will not be used for Poll mode */ if (roc_nix_inl_inb_is_enabled(nix))