From patchwork Tue Aug 9 10:53:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 114762 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B23C8A00C2; Tue, 9 Aug 2022 12:55:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A39842BC7; Tue, 9 Aug 2022 12:54:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B3DC642B86 for ; Tue, 9 Aug 2022 12:54:49 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2791THGS017221 for ; Tue, 9 Aug 2022 03:54:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OFqBPpzYZsQNOPVb+qATknD0l8FcnDI2I5YExfr7HhM=; b=P8Zy6bBb3ujp2qghw4GicDU3sd9wbf2JsKlVrnB1WjWynBYIejYwiemzsXqcjn9khMLs sHfWOuAm37JBdwvKxzGbQANV4vhIVXs77g1PRdgjlZk1zdZo2opLC1T2gKPO4JyiDMxo B6aWcjp6i9VRfYP8zKA3clM/1OsK7m49jFqTujJIZyyKSPacHHk1U9BCFFV/vMuNLHrx BbVD3McyFfMmzltBDtNQD73rlBUMUVrIeMdiyGND8sYu3ECXRJyYspZ5izvqll7JuGA/ Wi1BWkD/sg8ZJXcSDuISW9UjE19CbsopiyPnVo7Sc+/gTt95875iu9fs0u0O/gKw4N6M aA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hudy6spkr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Aug 2022 03:54:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 03:54:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 03:54:47 -0700 Received: from BG-LT92004.corp.innovium.com (unknown [10.193.69.70]) by maili.marvell.com (Postfix) with ESMTP id BDABC3F7048; Tue, 9 Aug 2022 03:54:44 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Volodymyr Fialko , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH v2 18/18] crypto/cnxk: add support for DOCSIS algorithm Date: Tue, 9 Aug 2022 16:23:56 +0530 Message-ID: <20220809105356.561-19-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809105356.561-1-anoobj@marvell.com> References: <20220808080606.220-1-anoobj@marvell.com> <20220809105356.561-1-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: go_AOOElWdAM2Agwt0UqJQUORbbCB_wr X-Proofpoint-ORIG-GUID: go_AOOElWdAM2Agwt0UqJQUORbbCB_wr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_03,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Volodymyr Fialko Add support for offloading RTE_CRYPTO_CIPHER_AES_DOCSISBPI and RTE_CRYPTO_CIPHER_DES_DOCSISBPI algorithms to symmetric crypto session. Signed-off-by: Volodymyr Fialko --- doc/guides/cryptodevs/features/cn9k.ini | 2 + doc/guides/rel_notes/release_22_11.rst | 1 + drivers/common/cnxk/roc_se.c | 25 ++++++++- drivers/common/cnxk/roc_se.h | 11 ++-- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 52 +++++++++++++++++++ drivers/crypto/cnxk/cnxk_se.h | 12 +++++ 7 files changed, 99 insertions(+), 6 deletions(-) diff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini index 98ad7cf10a..c3d131db1a 100644 --- a/doc/guides/cryptodevs/features/cn9k.ini +++ b/doc/guides/cryptodevs/features/cn9k.ini @@ -35,6 +35,8 @@ DES CBC = Y KASUMI F8 = Y SNOW3G UEA2 = Y ZUC EEA3 = Y +AES DOCSIS BPI = Y +DES DOCSIS BPI = Y ; ; Supported authentication algorithms of 'cn9k' crypto driver. diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index 333f66bef3..7fab9d6550 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -58,6 +58,7 @@ New Features * **Updated Marvell cnxk crypto driver.** * Added AES-CCM support in lookaside protocol (IPsec) for CN9K & CN10K. + * Added AES & DES DOCSIS algorithm support in lookaside crypto for CN9K. Removed Items diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c index 8d6446c3a0..2663480099 100644 --- a/drivers/common/cnxk/roc_se.c +++ b/drivers/common/cnxk/roc_se.c @@ -63,6 +63,7 @@ cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx, break; case ROC_SE_DES3_CBC: case ROC_SE_DES3_ECB: + case ROC_SE_DES_DOCSISBPI: fc_type = ROC_SE_FC_GEN; break; case ROC_SE_AES_CBC: @@ -70,6 +71,7 @@ cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx, case ROC_SE_AES_CFB: case ROC_SE_AES_CTR: case ROC_SE_AES_GCM: + case ROC_SE_AES_DOCSISBPI: if (unlikely(cpt_ciph_aes_key_validate(key_len) != 0)) return -1; fc_type = ROC_SE_FC_GEN; @@ -451,7 +453,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, uint8_t *zuc_const; uint32_t keyx[4]; uint8_t *ci_key; - int ret; + int i, ret; zs_ch_ctx = &se_ctx->se_ctx.zs_ch_ctx; @@ -531,6 +533,27 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad)); memcpy(fctx->hmac.ipad, &key[key_len], key_len); break; + case ROC_SE_AES_DOCSISBPI: + /* + * DOCSIS uses the combination of AES-CBC and residual termination blocks that are + * less than 128. Pass it as regular AES-CBC cipher to CPT, but keep type in + * se_ctx as AES_DOCSISBPI to skip block size checks in instruction preparation. + */ + cpt_ciph_aes_key_type_set(fctx, key_len); + fctx->enc.enc_cipher = ROC_SE_AES_CBC; + memcpy(fctx->enc.encr_key, key, key_len); + goto success; + case ROC_SE_DES_DOCSISBPI: + /* See case ROC_SE_DES3_CBC: for explanation */ + for (i = 0; i < 3; i++) + memcpy(fctx->enc.encr_key + key_len * i, key, key_len); + /* + * DOCSIS uses DES-CBC mode with special handling of residual termination blocks + * that are less than 64 bits. Pass it as regular DES-CBC, but keep type in + * se_ctx as DES_DOCSISBPI to skip block size checks in instruction preparation. + */ + fctx->enc.enc_cipher = ROC_SE_DES3_CBC; + goto success; case ROC_SE_SNOW3G_UEA2: if (chained_op == true) { struct roc_se_onk_zuc_chain_ctx *ctx = diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index d1a87a96da..e70a197d4f 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -10,6 +10,7 @@ #define ROC_SE_FC_MINOR_OP_ENCRYPT 0x0 #define ROC_SE_FC_MINOR_OP_DECRYPT 0x1 #define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10 +#define ROC_SE_FC_MINOR_OP_DOCSIS 0x40 #define ROC_SE_MAJOR_OP_HASH 0x34 #define ROC_SE_MAJOR_OP_HMAC 0x35 @@ -17,10 +18,10 @@ #define ROC_SE_MAJOR_OP_KASUMI 0x38 #define ROC_SE_MAJOR_OP_PDCP_CHAIN 0x3C -#define ROC_SE_MAJOR_OP_MISC 0x01 -#define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03 -#define ROC_SE_MISC_MINOR_OP_DUMMY 0x04 -#define ROC_SE_MISC_MINOR_OP_HW_SUPPORT 0x08 +#define ROC_SE_MAJOR_OP_MISC 0x01ULL +#define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03ULL +#define ROC_SE_MISC_MINOR_OP_DUMMY 0x04ULL +#define ROC_SE_MISC_MINOR_OP_HW_SUPPORT 0x08ULL #define ROC_SE_MAX_AAD_SIZE 64 #define ROC_SE_MAX_MAC_LEN 64 @@ -125,6 +126,8 @@ typedef enum { ROC_SE_AES_CTR_EEA2 = 0x92, ROC_SE_KASUMI_F8_CBC = 0x93, ROC_SE_KASUMI_F8_ECB = 0x94, + ROC_SE_AES_DOCSISBPI = 0x95, + ROC_SE_DES_DOCSISBPI = 0x96, } roc_se_cipher_type; typedef enum { diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index a3dcfbfa6d..588760cfb0 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -10,7 +10,7 @@ #include "roc_cpt.h" -#define CNXK_CPT_MAX_CAPS 35 +#define CNXK_CPT_MAX_CAPS 37 #define CNXK_SEC_CRYPTO_MAX_CAPS 14 #define CNXK_SEC_MAX_CAPS 9 #define CNXK_AE_EC_ID_MAX 8 diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index ffb0c289a0..1fb35f54cd 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -697,6 +697,49 @@ static const struct rte_cryptodev_capabilities caps_des[] = { }, }; +static const struct rte_cryptodev_capabilities caps_docsis[] = { + { /* AES DOCSIS BPI */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_DOCSISBPI, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 16 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* DES DOCSIS BPI */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_DES_DOCSISBPI, + .block_size = 8, + .key_size = { + .min = 8, + .max = 8, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, +}; + static const struct rte_cryptodev_capabilities caps_null[] = { { /* NULL (AUTH) */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -1158,6 +1201,12 @@ cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) } } +static void +cn9k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos) +{ + cpt_caps_add(cnxk_caps, cur_pos, caps_docsis, RTE_DIM(caps_docsis)); +} + static void crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], union cpt_eng_caps *hw_caps) @@ -1172,6 +1221,9 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, kasumi); CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, des); + if (!roc_model_is_cn10k()) + cn9k_crypto_caps_add(cnxk_caps, &cur_pos); + cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null)); cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end)); diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 33e65eb4e3..54a78d0a5a 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -2032,6 +2032,18 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) enc_type = ROC_SE_AES_ECB; cipher_key_len = 16; break; + case RTE_CRYPTO_CIPHER_AES_DOCSISBPI: + /* Set DOCSIS flag */ + sess->roc_se_ctx.template_w4.s.opcode_minor |= ROC_SE_FC_MINOR_OP_DOCSIS; + enc_type = ROC_SE_AES_DOCSISBPI; + cipher_key_len = 16; + break; + case RTE_CRYPTO_CIPHER_DES_DOCSISBPI: + /* Set DOCSIS flag */ + sess->roc_se_ctx.template_w4.s.opcode_minor |= ROC_SE_FC_MINOR_OP_DOCSIS; + enc_type = ROC_SE_DES_DOCSISBPI; + cipher_key_len = 8; + break; case RTE_CRYPTO_CIPHER_3DES_CTR: case RTE_CRYPTO_CIPHER_AES_F8: case RTE_CRYPTO_CIPHER_ARC4: